16-bit advanced control timer (TIM1) RM0016
196/449 Doc ID 14587 Rev 8
Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIM1_CCR1 disabled. TIM1_CCR1 can be written at anytime. The new value
is taken into account immediately.
1: Preload register on TIM1_CCR1 enabled. Read/write operations access the preload register.
TIM1_CCR1 preload value is loaded in the shadow register at each UEV.
Note: These bits can no longer be modified while LOCK level 3 has been programmed (LOCK bits in
TIM1_BKR register) and CC1S = 00 (the channel is configured in output).
For correct operation, preload registers must be enabled when the timer is in PWM mode. This
is not mandatory in one-pulse mode (OPM bit set in TIM1_CR1 register).
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on the counter and CCR1 values, even when the trigger is on.
The minimum delay to activate CC1 output when an edge occurs on the trigger input, is 5 clock
cycles.
1: An active edge on the trigger input acts like a compare match on the CC1 output. If this happens,
OC is set to the compare level irrespective of the result of the comparison. The delay to sample the
trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel
is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0]: Capture/compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1FP1
10: CC1 channel is configured as input, IC1 is mapped on TI2FP1
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an internal
trigger input is selected through the TS bit (TIM1_SMCR register).
Note: CC1S bits are writable only when the channel is off (CC1E = 0 in TIM1_CCER1).
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