3.3.8 Indirect Access
of
External Bus Controller DCRs
The
following
procedure
accesses
the
ESC
DCRs
listed
in
Table
3-9.
1.
Write
the
offset
from
Table
3-10
to
the
Peripheral
Controller
Address
Register
{EBCO_CFGADDR}.
2.
Read
data
from
or
write
data
to
the
Peripheral
Controller
Data
Register
{EBCO_CFGDATA}.
Table 3·9. External Bus Controller
DCR
Usage
DCR
Register
Number
Access
Description
EBCO_CFGADDR
Ox012
RIW Peripheral Controller Address Register
EBCO_CFGDATA
Ox013
RIW
Peripheral Controller Data Register
Table 3·10. Offsets for External Bus Controller Registers
Register
Offset
Access
Description
EBCO_BOCR
OxOO
RIW
Peripheral Bank ° Configuration Register
EBCO_B1CR
Ox01
RIW
Peripheral Bank 1 Configuration Register
EBCO_B2CR
Ox02
RIW Peripheral Bank 2 Configuration Register
EBCO_B3CR
Ox03
RIW Peripheral Bank 3 Configuration Register
EBCO_B4CR
Ox04
RIW Peripheral Bank 4 Configuration Register
EBCO_B5CR
Ox05
RIW Peripheral Bank 5 Configuration Register
EBCO_B6CR
Ox06
RIW Peripheral Bank 6 Configuration Register
EBCO_B7CR
Ox07
RIW
Peripheral Bank 7 Configuration Register
EBCO_BOAP
Ox10
RIW
Peripheral Bank ° Access Parameters
EBCO_B1AP
Ox11
RIW Peripheral Bank 1 Access Parameters
EBCO_B2AP
Ox12
RIW Peripheral Bank 2 Access Parameters
EBCO_B3AP
Ox13
RIW Peripheral Bank 3 Access Parameters
EBCO_B4AP
Ox14
RIW Peripheral Bank 4 Access Parameters
EBCO_B5AP
Ox15
RIW
Peripheral Bank 5 Access Parameters
EBCO_B6AP
Ox16
RIW Peripheral Bank 6 Access Parameters
EBCO_B7AP
Ox17
RIW
Peripheral Bank 7 Access Parameters
EBCO_BEAR
Ox20
RIW
Peripheral Bus Error Address Register
EBCO_BESRO
Ox21
RIW
Peripheral Bus Error Status Register 0
EBCO_BESR1
Ox22
RIW
Peripheral Bus Error Status Register 1
EBCO_CFG
Ox23
RIW
External Peripheral Control Register
3-20
PPC405GP User's Manual
Preliminary
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