9.2
Pin
Sharing
The PPC405GP uses pin (ball) multiplexing (sharing) to reduce the total pin requirement without
significantly reducing functionality.
Some of the pins that are multiplexed require OCR register
programming to configure the pin for the desired function.
It is expected that
in
an application, a
particular pin is programmed to serve one function. While nothing prevents changing the function of a
pin during operation, most
applications configure a pin once at power-on reset (POR). Table
9-1
lists
the multiplexed PPC405GP signals and indicates the OCR bit that controls the pin. The default signal
appears first and the alternate signal is
in
brackets.
Table 9·1. Multiplexed Pins
Signal DCR Bit
Description
GPI01
[TS1
E]
CPCO_CRO[TRE] Set of GPIO pins that can be reconfigured for use as
GPI02[TS2E]
the CPU Trace interface.
GPI03[TS10]
GPI04[TS20]
GPIOS[TS3]
GPI06[TS4]
GPI07[TSS]
GPI08[TS6]
GPI09[TrcClk]
PerCS1[GPI010] CPCO_CRO[G10E] Peripheral
Chip selects that can be reconfigured for
PerCS2[GPI011] CPCO_CRO[G11
E]
use as GPIOs.
PerCS3[GPI012]
CPCO_CRO[G12E]
PerCS4[GPI013] CPCO_CRO[G13E]
PerCSS[GPI014] CPCO_CRO[G14E]
PerCS6[GPI01S] CPCO_CRO[G1SE]
PerCS7[GPI016] CPCO_CRO[G16E]
IROO[GPI017] CPCO_CRO[G17E] External Interrupts
that can be reconfigured for use
IR01 [GPI018] CPCO_CRO[G18E]
as GPIOs.
IR02[GPI019]
CPCO_CRO[G19E]
IR03[GPI020]
CPCO_CRO[G20E]
IR04[GPI021]
CPCO_CRO[G21
E]
IROS[GPI022] CPCO_CRO[G22E]
IR06[GPI023]
CPCO_CRO[G23E]
Preliminary Pin
Strapping and Sharing
9-3
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