Since
an
uncorrectable error also results
in
an error signal to the master that initiated the transfer,
other side effects may occur. For example, an instruction fetch with an uncorrectable error causes a
machine check.
In the case of a DMA transfer, the DMA channel stops and an error is logged.
15.4.4 Error Locking
The PCI Bridge and Media Access Layer (MAL) controllers may qualify their PLB transactions to the
SDRAM Controller such that the information describing any errors that occur during these transfers
becomes locked. When an error is locked, subsequent errors are not permitted to overwrite the
information detailing the first error.
When a master requests error locking an error locks not only the SDRAMO_BESRn field for the
master, but also SDRAMO_BEAR. These remain locked until software clears them. The SDRAM
Controller has a SDRAMO_BESRn field for each PLB master containing two bits associated with error
locking.
One is the field lock bit and the other is the address lock bit. When an error
is
detected with
locking enabled the field lock bit is set to a value of one. Setting the field lock bit prevents subsequent
errors for this master from being logged and overwriting the contents of the field.
In
addition, the
address lock bit is set if no other master has previously locked the SDRAMO_BEAR.
Once the
SDRAMO_BEAR is locked, no future errors from this or any master can update the SDRAMO_BEAR
until software clears the lock bits. When software processes an error it should clear the error status
and both lock bits at the same time.
15.4.5
ECC
Error Status Register (SDRAMO_ECCESR)
The ECC Error Status Register (SDRAMO_ECCESR) tracks ECC related errors encountered during
SDRAM memory accesses. Bits
in
SDRAMO_ECCESR are cleared by writing a 32-bit value to
SDRAMO_ECCESR with a 1 in any bit position that is to be cleared and
°
in
all other bit positions.
BLnCE
CE
BKnE
+
~
~
1
0
31
4
15116
19
1
2
0
311
t t
CBE
UE
Figure 15-13. ECC Error Status Register (SDRAMO_ECCESR)
0:3 BLnCE Byte Lane n Corrected Error
o No error
1 Error occurred
in
byte lane n
4:7
' ......
Reserved
>
....
,
.......
,.
8:9 CBE
Error Detected
in
Check bits
00 No error
01
Error
in
lower check bits
10 Error in upper check bits
11
Error
in
both sets of check bits
10
CE Correctable Error
11
UE Uncorrectable Error
12:15
............
.
..........
,
..
'
..
.....
,.,
Reserved
15-16
PPC405GP User's
Manual
Preliminary
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