The term "single-beat" refers to the M_size = 0000 transaction type. PCI slave devices are referred to
as
"targets."
PCI
bridge initiates the following PLB master commands:
• 8-Byte Read:
Generated
in
response to single beat
or
burst Memory Read commands from the PCI bus.
• Doubleword Burst Read:
Generated
in
response to Memory Read Line and Memory Read Multiple commands on the PCI
bus. PCI bridge can also be programmed to perform doubleword bursts
on
behalf of Memory Read.
• 1-8-Byte Write:
Generated
in
response to single-beat
(1-4
byte) Memory Write commands
on
the PCI bus; also
generated when the PCI master uses non-contiguous byte enables (see "Byte Enable Handling" on
page 17-17).
• Doubleword Burst Write:
Generated in response to burst Memory Write and Memory Write and
Invalidate commands on the
PCI bus.
The PLB treats Memory Write and Memory Write and
Invalidate identically (nothing on the PLB
distinguishes a Memory Write from a Memory Write and
Invalidate.)
PCI
bridge does not generate line reads or line writes on the PLB.
17.4.2.2 Handling
of
Reads from
PCI
Masters
PCI
bridge responds to PCI Memory Read, Memory Read Line, and Memory Read Multiple
commands. The PCI bridge initiates all PLB reads as single-beat
or
doubleword burst transfers.
Memory Read generates a PLB
single-beat doubleword read. Memory Read Line and Memory Read
Multiple commands generate PLB doubleword bursts. For Memory Read Line, PCI bridge encodes a
burst
length on the byte enable pins of the PLB that corresponds to the number of doublewords from
the start address to the end of a word boundary and terminates when the encoded number of words
has been transferred. This is
called a PLB fixed length burst. If the starting address is the last
doubleword
on a word boundary (typically, this should not occur), PCI bridge executes a single-beat
read. For Memory Read Multiple,
PCI
bridge sets the byte enables to
Os,
indicating a variable length
burst.
The
PCI target can be programmed to treat Memory Reads as Memory Read Line commands
or
Memory Read Multiple commands
in
terms of PLB read behavior.
The
PCI bridge guarantees the PCI initial target latency requirement by retrying the PCI cycle if read
data is not
immediately available
in
the read buffer. Subsequent latency is programmable using
PCICO_BRDGOPT2[STLD].
The PCI bridge master latency timer can limit the length of read bursts using
PCICO_BRDGOPT1 [MLTC]. The timer limits the duration of a burst to the programmed value
in
units
of PLB
clock cycles.
Preliminary
PCI Interface 17-15
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