Table 16-4. Signal States During Hold Acknowledge (HoldAck=1)
Signal
Name State Usage
PerAddrO:31
Input Requested address from external master.
PerWBEO:3
Input Selects the requested byte(s) for reads and writes.
PerRIW Input
Determines if the operation is a read or write.
PerBLast
Input Active during single transfers and the last transfer of a burst.
PerDataO:31
I/O
Read and write data.
PerOE High-Z
Unused.
PerWE 1
Unused.
PerErr
High-Z
Unused.
PerParO:3
High-Z
Unused.
16.5.2 Transaction Overview
The EBM interface supports direct attachment of 8-, 16-, and 32-bit masters. By programming the
width of the
external master into EBCO_CFG[EMS] the interface accepts write data and provides read
data at the appropriate width for the master. The EBM interface
includes a 32-byte data buffer, used
for both read and write operations between the EBM and PLB- and
OPB-mapped memory locations.
While write operations only use the buffer during bursts, all reads prefetch one doubleword and burst
reads prefetch EBCO_CFG[BPR]
doublewords from the source memory into the buffer. This
prefetched data remains
in
the buffer until either a write operation is performed or a read is requested
to a different 32-byte
block
o~
memory.
To
provide the best possible performance, the EBM interface supports both single and burst
transactions.
Single read transfers result
in
the EBM reading and buffering a 64-bit doubleword from
the requested memory address. The requested read data is then serviced from within this
doubleword. If the next operation on the EBM interface is a read and targets this same doubleword, it
is serviced
directly from the buffer. Burst reads are similar, except that the EBM prefetches four
doublewords beginning with the requested word.
Single write transfers result
in
a separate PLB transaction for each data item.
To
improve
performance, burst writes are gathered in the 32-byte buffer and forwarded in a
single PLB
transaction to the target memory.
16.5.3 Single Read and Single Write Transfers
Figure 16-12 illustrates external master bus arbitration along with a single read and signal write
transfer. An
external master requests ownership of the peripheral bus by driving HoldReq active along
with the desired priority on HoldPri. Observe that HoldPri must be held at constant value throughout
the entire
external master tenure. After two or more PerClk cycles the arbiter will grant the peripheral
bus to the external master. The delay from when the external master asserts HoldReq to when
HoldAck becomes active is variable and depends on any EBC transaction that may be in progress
or
pending, the level on HoldPri, and the programming in EBCO_CFG[EMPL] and EBCO_CFG[EMPH].
Once the external master is granted the peripheral bus (HoldAck=1), it may either directly control a
device on the EBC or issue read and write transactions to the
external master interface. This
waveform and the ones that
follow apply only to the later case. Additionally, cycles shown with breaks
in
the clock may not be present
or
may extend for multiple cycles.
External Bus Controller 16-19
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