IBM PowerPC 405GP User Manual

21 DWE Debug Wait Enable
o Debug wait mode is disabled.
1 Debug wait mode is enabled.
22
DE
Debug Interrupts Enable
o Debug interrupts are disabled.
1 Debug interrupts are enabled.
23:25 Reserved
26
IR Instruction Relocate
o Instruction address translation is
disabled.
1 Instruction address translation is
enabled.
27 DR Data Relocate
o Data address translation is disabled.
1 Data address translation is enabled.
28:31 'Reserved
10.11.2 Save/Restore Registers 0 and 1 (SRRO-SRR1)
SRRO and SRR1 are 32-bit registers that hold the interrupted machine context when a noncritical
interrupt is processed.
On interrupt, SRRO is set to the current or next instruction address and the
contents of the
MSR are written to SRR1. When an rfi instruction is executed at the end of the
interrupt handler, the program counter and the
MSR are restored from SRRO and SRR1, respectively.
The contents of
SRRO and SRR1 can be written into GPRs using the mfspr instruction. The contents
of GPRs can be written to SRRO and SRR1 using the mtspr instruction.
Figure
10-10 shows the bit definitions for SRRO.
1
0
29[30 311
Figure 10-10. Save/Restore Register 0 (SRRO)
0:29
SRRO receives an instruction address when a non-critical interrupt is taken;
the
Program Counter is restored from SRRO when rfi executes .
30:31
....
Reserved
Figure 10-11 shows the bit definitions for SRR1.
Preliminary Interrupt Controller Operations
10-29

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English