IBM PowerPC 405GP

The SDRAM uses a 32-bit, PC100 memory interface configured for CAS latency of 2, command
leadoff of 2, and RAS to CAS delay (T
rcd
)
of 2. All memory accesses are page idle, unless indicated
otherwise.
Note: The PLB signals shown in the following timing diagrams are not externally accessible. They are
included for information purposes and as an aid to understanding the PCI operations. For more
information on these
signals, refer to Processor Local Bus Architecture Specifications.
17.10.1 PCI Timing Diagram Descriptions
The following sections briefly describe each of the timing diagrams that follow the descriptions. Each
description covers both the asynchronous and synchronous
clocking modes for that operation. The
timing diagrams then follow with all of the asynchronous diagrams grouped together followed by all of
the synchronous diagrams grouped
to!;Jether.
17.10.1.1 PCI Master Burst Read From SDRAM
Figure 17-60 (asynchronous) and Figure 17-67 (synchronous) show a PCI Master executing a 128-
byte Read
Multiple from SDRAM. PCI bridge retries the initial request and performs a delayed read.
PCI bridge executes a variable-length, doubleword read burst on PLB to SDRAM, filling its 96-byte
read buffer. The read is a page hit. When the
PCI master re-requests its read, PCI bridge begins
bursting out of its read buffer,
while continuing to prefetch from SDRAM.
17.10.1.2 PCI Master Burst Write To SDRAM
Figure 17-61 and Figure 17-68 show a PCI Master executing a 128-byte Write to SDRAM. PCI bridge
accepts
several beats of data into its 64-byte write buffer before executing variable-length,
doubleword
write bursts on PLB to SDRAM. The final write burst is fixed-length, since the PCI write
has
completed, and PCI bridge knows the exact burst length.
17.10.1.3 CPU Read From PCI Memory Slave, Nonprefetching
In Figure 17-62 and Figure 17-69, a PLB Master (CPU) executes a single-beat 64-bit read from a
region of
PCI memory marked as nonprefetchable. PCI bridge responds as a 32-bit PLB slave, so the
CPU executes conversion
cycles for each read. PCI bridge executes a single-beat PCI read for both
PLB read requests.
17.10.1.4 CPU Read From PCI Memory Slave, Prefetching
In Figure 17-63 and Figure 17-70, a PLB Master (CPU) executes 8, 64-bit, single-beat reads from a
region of
PCI memory marked as prefetchable. The first PLB read causes PCI bridge to execute a 64-
byte Read
Multiple to fill its 64-byte read prefetch buffer. The data for subsequent PLB reads is
provided from the read buffer and no
PCI cycles are generated. PCI bridge responds as a 32-bit PLB
slave, so the CPU executes conversion cycles for each read.
17.10.1.5 CPU Write To PCI Memory Slave
Figure 17-64 and Figure 17-71 show a PLB Master (CPU) executing 4, 64-bit, single-beat writes to
PCI memory. PCI bridge responds as a 32-bit slave, so the CPU executes conversion cycles for each
write.
PCI bridge posts the writes in its 4-entry write buffer, and executes a PCI single-beat Memory
Write for each request.
Preliminary
PCI Interface 17-65