IBM PowerPC 405GP User Manual

The PRR field of the Exception Syndrome Register (ESR) is set when an interrupt was caused by a
privileged instruction program exception. Software is not required to
clear ESR[PRR].
3.9.2 Privileged Instructions
The instructions listed in Table 3-20 are privileged and cannot be executed while in user mode
(MSR[PR]
= 1).
Table 3-20. Privileged Instructions
dcbi
dccci
dcread
iccci
icread
mfdcr
mfmsr
mfspr
For all SPRs except CTR, LR, SPRG4-SPRG7, and XER. See
"Privileged SPRs" on page 3-42
mtdcr
mtmsr
mtspr
For all SPRs except CTR, LR, XER. See "Privileged SPRs" on page 3-42
rfci
rfi
tibia
tlbre
tlbsx
tlbsync
tlbwe
wrtee
wrteei
3.9.3 Privileged SPRs
All SPRs are privileged, except for the LR, the CTR, the XER, USPRGO, and read access to SPRG4-
SPRG7. Reading from the time base registers Time Base Lower (TBL) and Time Base Upper (TBU)
is not
privileged. These registers are read using the mftb instruction, rather than the mfspr
instruction. TBL and TBU are written (with different addresses) using mtspr, which is privileged for
these registers. Except for moves to and from
non-privileged SPRs, attempts to execute mfspr and
mtspr instructions while in user mode result in privileged violation program exceptions.
3-42 PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English