- PerCSn may not go inactive between the back-to-back transfers.
-
If EBCO_BnAP[OEN]=O, PerOE may not become inactive between the two transfers.
-
If EBCO_BnAP[WBN]=O and EBCO_BnAP[WBF]=O, PerWBEO:3 may not go inactive between
the back-to-back transfers.
16.3.1 Burst Read Transfer
Figure 16-5 shows the peripheral interface timing for a burst read transfer from a burst enabled
(EBCO_BnAP[BME]=1)
bank. The transaction begins with the address being driven. If byte enable
mode is enabled for the bank (EBCO_BnAP[BEM]=1) the byte enables are also output concurrently
on
PerWBEO:3. PerCSn then becomes active EBCO_BnAP[CSN] cycles after the address, while
PerOE
goes low EBCO_BnAP[OEN] cycles after PerCSn. The EBC then waits until
EBCO_BnAP[FWT]+
1 cycles have elapsed since the start of the transaction and then reads the data
bus and the peripheral error input,
PerErr. If parity checking is enabled (EBCO_BnAP[PEN]=1) the
parity is
also read at this same time.
The next address of the burst is then driven and after
EBCO_BnAP[BWT]+ 1 cycles the EBC performs
the next read. The remaining items in the burst are read in the same manner, except that
PerBLast is
active during the
last data element. The EBC then drives PerCSn, PerOE and PerBLast high and
waits
EBCO_BnAP[TH] cycles before allowing any pending transfers to occur.
BEM=O
Cycle
ITIjtntntntntntnQJL
PerClk
rLr}U1U1U1U1U1U1U"L
PerAddrO:31
PerCSn
PerRiW
:
OEN
1+-+1
PerDE
=..J
\
PerBLast
=..J
[ PerWBEO:3
=..J
PerWE
=..J
[ PerWBEO:3
BEM=1
__
=----:J
PerWE
PerDataO:31
PerParO:3
PerErr
Figure 16-5. Burst Read Transfer
External Bus Controller 16-9
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