8.9.1 OCM Initialization
The following information applies if OCM is to be accessed.
If instruction-side OCM is to be accessed, the OCM Instruction-Side Address Range Compare
Register
(OCMO_ISARC) must be initialized to locate the instruction-side OCM address space
in
the
PPC405GP address map.
If
data-side OCM is to be accessed, the OCM Data-Side Address Range
Compare Register
(OCMO_DSARC) must be initialized to locate the data-side OCM address space
into the
PPC405GP address map. "OCM Addressing" on page
5-1
provides details of the instruction-
side
OCM and data-side OCM address spaces. See "Memory Organization and Addressing" on
page
3-1
for information about the PPC405GP memory map.
8.9.1.1 Initializing Instruction-Side
OCM
The following procedure describes the steps to be taken If instruction-side OCM is to be accessed.
1.
Set the ISEN field of the OCM Instruction-Side Control Register to disable instruction-side OCM
accesses (OCMO_ISCNTL[ISEN] = 0).
2.
To
ensure that interrupts do not interfere with the instruction cache array invalidation performed
in
step 4, set MSR[EE] = ° and MSR[CE] to mask interrupts. This prevents a potential problem
caused by dirty cache addresses that would not be fetched from the cache because they are
marked as
non-cachable.
3.
Mark the address region to be programmed as OCM address space as non-cachable.
4.
Invalidate the instruction cache array to ensure that no addresses to· be programmed as OCM
addresses are
in
the cache. The ieeei instruction invalidates the instruction cache array.
5.
Modify the value
in
OCMO_ISARC.
6.
Set OCMO_ISCNTL[ISEN] = 1 to enable instruction-side OCM accesses. Also, set
OCMO_ISCNTL[ISTCM] = 0.)
OCMO_ISCNTL[ISTCM] should
be initialized to ° to take the instruction-side OCM controller out of
two
cycle mode, the default mode after a reset. This enables instruction-side fetches to complete
in
a
single cycle, providing the same performance as cache hits. See "OCM Instruction-Side Control
Register (OCMO_ISCNTL)" on page 5-6 for details.
8.9.1.2 Initializing Data-Side OeM
The following procedure describes the steps to be taken if data-side OCM is used to load the initial
contents of instruction-side OCM,
or
if data-side OCM is to be accessed.
1.
Set the DSEN field of the Data-Side Control Register to disable data-side OCM accesses
(OCMO_DSCNTL[DSEN] = 0).
2.
To
ensure that interrupts do not interfere with the data cache array invalidation performed
in
step 4,
set MSR[EE]
= ° and MSR[CE] to mask interrupts. This prevents a potential problem caused by
dirty cache addresses that
would not be fetched from the cache because they are marked as non-
cachable. .
3.
Mark the address region that is to be programmed as OCM address space as non-cachable.
4. Invalidate the data cache array to ensure that no addresses to be programmed as OCM addresses
are in the cache. Use a sequence of
debt
instructions to invalidate the data cache.
Preliminary Reset and Initialization
8-13
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