IBM PowerPC 405GP

Contents
Figures ..................................•................ : ............................................................................... xxix
Tables ......•..............................................................................................•..................................
xli
About This Book ............................................................................................................. : ..... xlvii
Who Should Use This Book ......................................................................................... """"'"'''''''''''''''''''''''' xlvii
How to Use This Book .................................................................................................................................... xlvii
Conventions ................................................................................................................................................... xlviii
Part I. Introducing the PPC405GP Embedded Processor ................................................... 1-1
Chapter 1. Overview ............................................................................................................... 1-1
PPC405GP Features """'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' .......................................... 1-2
Bus and
Peripheral Features ....................................................................................................................... 1-2
PowerPC Processor Core Features ............................................................................................................ 1-3
PowerPC Architecture .""""".""""""""" .. """"""." .. """".""".""""" ... """"""."" ....................................... 1-4
The
PPC405GP as a PowerPC Implementation .............................................................................................. 1-5
RISC Processor Core Organization ................................................................................. ; ............................... 1-5
Instruction and Data Cache Controllers ....................................................................................................... 1-5
Instruction Cache Unit ............................................................................................................................ 1-6
Data Cache Unit
.. """ .. """""" .. """"""".""."."".""."" ... """"""""."""" ............................................ 1-6
Memory Management Unit .......................................................................................................................... 1-6
Timer
Facilities ............................................................................................................................................ 1-8
Debug .......................................................................................................................................................... 1-8
Development Tool Support """""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' .......................... 1-8
Debug Modes
""""""".""""""""".""".""".".".""".""".""""" .. """""" ............................................. 1-9
Processor Core Interfaces ............................. ""'" ............................ """"'"'''''''''''''''' ........................... ..... 1-9
Processor Local Bus ...................................................................................... "".""." .. """".""""""." ... 1-9
Device
Control Register Bus ................................................................................................................... 1-9
Clock and Power Management ""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ........................ 1-9
JTAG ....................................................................................................................................................... 1-9
Interrupts .. """'"'''''''''' ......................................... """"" ........ "" .. " .. " .. ".. ............ ....... ........ ..... .............. 1-9
On-Chip Memory .................................................................................................................................... 1-9
Processor Core Programming Model ............................................................................................................... 1-9
Data Types ................................................................................................................................................ 1-10
Processor Core Register Set Summary .................................................................................................... 1-10
General Purpose Registers ................................................................................................................... 1-10
Special Purpose Registers ...................................... ""."... .............................. ..................................... 1-10
Machine State Register ........................................................................................................................ 1-10
Condition Register
"""""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ......................................... 1-11
Device Control Registers .......... """""""""".".""."" .. ".""." ... ".""." .. "" ............................ """""""" 1-11
Memory-Mapped 1/0 Registers """""""""""""""'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ....................... 1-11
Addressing Modes ..................................................................................................................................... 1-11
Chapter 2. On-Chip Buses ..................................................................................................... 2-1
Processor Local Bus ........................................................................................................................................ 2-1
PLB Features .............................................................................................................................................. 2-2
PLB Masters and Slaves ............................................................................................................................. 2-2
PLB Master Assignments ............................................................................................................................ 2-2
PLB Transfer Protocol """""""."""""."""""" ... """""." .. """."""" .. """"."""."" .................................... 2-3
Overlapped PLB Transfers .......................................................................................................................... 2-4
PLB Arbiter Registers """'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ............................................. 2-5
PLB Arbiter Control Register (PLBO_ACR) ............................................................................................. 2-5
PLB Error Address Register (PLBO_BEAR) ............................................................................................ 2-5
Preliminary Contents
v