PLB Error Status Register (PLBO_BESR) .............................................................................................. 2-6
PLB to OPB Bridge Registers . ..... ... ........ ..... .... ........ ................. ............... ...... ......... ......
...
...... ..................... 2-8
Bridge Error Address Register
(POBO_BEAR) ....................................................................................... 2-8
Bridge Error Status Registers
(POBO_BESRO-POBO_BESR1) ............................................................ 2-8
On-Chip Peripheral Bus ................. .................. .......... .... ....... ......... .... ......... ........ ................ .............. ...
2-11
OPB Features ...........................................................................................................................................
2-11
OPB Master Assignments ......................................................................................................................... 2-12
OPB Arbiter Registers ............................................................................................................................... 2-12
OPB Arbiter Control Register (OPBAO_CR) ......................................................................................... 2-12
OPB Arbiter Priority Register (OPBAO_PR) ......................................................................................... 2-13
Part
II.
The PPC405GP RiSe Processor ...............................................................................
11-1
Chapter 3. Programming Model ............................................................................................ 3-1
User and Privileged Programming Models ......................................................................................................
3-1
Memory Organization and Addressing ............................................................................................................
3-1
Physical Address Map ...... ......... ..... .................................. ........ .... ................... ........
...
............. .............. ..... 3-2
Storage Attributes ........... ............. ...................................... ........................ ......... ........................................ 3-3
Registers ................... ........ ..................
...
..... ......... .......................................... .......... ........... .................. .......... 3-3
General Purpose Registers (RO-R31) .................................................... ......................................... ............ 3-6
Special Purpose Registers.................... ........... ..... ... ................................ ...... ....... ............ ..... ............ ......... 3-6
Count Register (CTR)
...
...................... ....... .......... ................................ ...... ......... ...... .... .....
...
........... ....... 3-7
Link Register (LR) ....... ................... ................... .......................... ..... .................. ..... .... ..... ................ ..... 3-8
Fixed
Point Exception Register (XER) ...............
...
............. .............. ................... ....... ....... ................ ..... 3-8
Special Purpose Register General (SPRGO-SPRG7) .........................................................................
3-11
Processor Version Register (PVR) ....................................................................................................... 3-12
Condition Register (CR) ............................................................................................................................ 3-12
CR
Fields after Compare Instructions .................................................................................................. 3-13
The
CRO
Field ...................................................................................................................................... 3-14
The Time Base .......................................................................................................................................... 3-15
Machine State Register (MSR) ................................................................................................................. 3-15
Device
Control Registers .......................................................................................................................... 3-16
Directly Accessed DCRs ...................................................................................................................... 3-17
Indirectly Accessed DCRs .................................................................................................................... 3-19
Indirect Access of SDRAM Controller DCRs ............................................................................................ 3-19
Indirect Access of External Bus Controller DCRs ..................................................................................... 3-20
Indirect Access of Decompression Controller DCRs ................................................................................
3-21
Memory-Mapped Input/Output Registers .................................................................................................. 3-22
Directly Accessed MMIO Registers ..................................................................................................... 3-22
Indirectly Accessed MMIO Registers ................................................................................................... 3-25
Data Types and
Alignment ............................................................................................................................ 3-26
Alignment for Storage Reference and Cache Control Instructions ........................................................... 3-27
Alignment and Endian Operation ....... ..... ..... .... ......... ......... ....... .... ................... ........ ........ ...................... ... 3-27
Summary of
Instructions Causing Alignment Exceptions ......................................................................... 3-28
Byte Ordering ........ ...... ......... ......... ....... ...... ......... ................... .......... ......... .......... ........ ..... .... ....... .............. ... 3-28
Structure Mapping
Examples .......... ... ..... ..... .... .................. ........... ......... .................. .....
...
...... .............. ..... 3-29
Big Endian Mapping ..... ......... ........ ..... ..... .... .................. ....... ............................... ..... .... ................... ..... 3-29
Little Endian Mapping .................... ..... ......... ................. ........ ..... ........ ....................... .... ................... ..... 3-30
Support for Little Endian Byte Ordering .................................................................................................... 3-30
Endian (E) Storage Attribute ........... ........ ............ ............ .... ........... ......... ....... ......... .......... .....
...
........ ........ 3-30
Fetching
Instructions from Little Endian Storage Regions ................................................................... 3-31
Accessing Data in Little Endian Storage Regions ................................................................................
3-31
PowerPC Byte-Reverse Instructions .................................................................................................... 3-32
Instruction Processing ................................................................................................................................... 3-33
Branch
Processing . ....... ......... ................ ....... ................... ................................ ...
...
......... ...................... ........ 3-34
Unconditional Branch Target Addressing
Options .................................................................................... 3-34
Conditional Branch Target Addressing Options ....... .... .... .......................... ........ ......... ........................... ... 3-35
vi PPC405GP User's Manual
Preliminary
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