Chapter 14. Decompression Controller Operation
The decompression controller enables PPC405GP instructions to be stored in memory
in
a
compressed form, thus, reducing memory requirements and overall system cost. Because the
processor core cannot execute compressed instructions, hardware is provided
to
decompress the
compressed instructions. The decompression controller decompresses instructions on-the-fly, as the
processor core fetches instructions from memory. The decompression unit is located
in
the path
between memory and the processor core.
When decompressed instructions are stored in the instruction cache unit
(ICU), the performance
penalty is minimized.
Increased latency occurs only when instruction fetches miss in the cache.
Average latency is further reduced by a buffer
in
the decompression hardware that holds more
instructions than are requested by the
CPU. If a subsequent fetch occurs to a nearby memory location
that is already
in
the buffer, data is returned from the buffer; no memory cycle is required. In such
cases, initial latency is
less than a normal uncompressed fetch from memory.
Code to be stored
in
compressed form is compressed by software after compiling and before loading.
Thus, code compression can be performed once by the application developer. The compressed code
is
in
the load image.
The decompression controller, located between the processor core and memory, is transparent to the
processor core. When the processor core performs an instruction fetch, the decompression
controller
works with the memory controller (SDRAM
or
external bus controller [EBC)) to provide a
decompressed instruction stream to the
CPU. The memory controllers deliver the compressed stream
of instructions to the decompression
controller, which decompresses the instructions and delivers the
resulting instruction stream to the processor core.
14.1
Code Compression
~nd
Decompression
While code decompression is performed
in
hardware when the processor core fetches instructions in
a compressed code address space, code compression is performed
only once, between the compile
and
load steps
in
the usual programming sequence.
14.1.1 Code Compression
Compression software analyzes compiled code, finds the set of most frequently used instructions,
and builds decode tables from those instructions.
The compression software splits each instruction, analyzes the upper and
lower halfwords of the
instruction to find the most common 16-bit patterns. The most frequently used patterns are tagged for
insertion
in
a decode table. Infrequently used instructions are tagged as not compressed. The 16-bit
patterns that match those
in
the decode table are stored in the compressed code image, along with
uncompressed instructions. The decode
table is loaded into the decompression controller before
attempted execution of the compressed instruction streams.
After the decode table is built, a compiled code image is compressed, using a scheme employing a
tag and an index. The decompression controller generates an address into the decode table to select
the original 16-bit pattern.
Preliminary
Decompression Controller Operation
14-1
To Next Page
Loading...
Need help?
General
