IBM PowerPC 405GP User Manual

17.4.1.2 PLB Slave Read Handling
PLB master read requests are decoded into four types: PCI Memory, liD, Configuration, and Interrupt
Acknowledge. If the request falls within any of these ranges, and is a supported command type, the
bridge claims the cycle
initially by asserting a PLB wait signal (as opposed to a PLB address
acknowledge signal). The bridge must first gain access to the
PCI bus before acknowledging a PLB
read request. The specific timing of the address acknowledge is dependent upon the type of transfer.
All posted writes must be flushed before a read is allowed to complete.
For PLB
line reads, the PCI bridge must wait for all read data to be received before acknowledging the
PLB request. This is because
PCI targets are allowed to disconnect in the l1}iddle of a transfer, and
the PLB requires line transfers to be atomic.
If the system can guarantee that PCI targets do not
disconnect these reads,
PCICO_BRDGOPT1 [APLRM] can be set to 1. In this mode, line read
performance is improved by having the bridge PLB slave assert an address acknowledge signal and
begin its data tenure as soon as the first word is received on the
PCI bus.' If the above guarantee
cannot be made, the setting of this bit could hang the bridge.
If the PCI cycle Master Aborts, all beats of read data are returned as OxFFFFFFFF.
PLB master reads to the
PCI bridge configuration registers are allowed to execute regardless of
whether any write data is posted in the bridge. The configuration registers are described in
"PCI
Bridge Configuration Registers" on page 17-19.
17.4.1.3 Prefetching
When the PCI bridge receives a PLB 1-S-byte or byte or halfword burst read request that decodes to
a PMM marked as nonprefetchable. The
PCI bridge runs a single beat read to the PCI. If the PCI
cycle is retried, the PLB cycle is rearbitrated.
When the
PCI bridge receives a PLB 1-S-byte or byte or halfword burst read request that decodes to
a PMM marked as prefetchable, the
PCI bridge burst reads up to a 64 bytes from the PCI and saves
the data
in the PLB slave read prefetch buffer. Less than 64 bytes can be read if the PCI target
disconnects,
or if the PCI bridge PCI master disconnects due to a master latency time out. Note that
PCI bridge prefetching is not affected by memory management page boundaries (PLB_Guarded is
ignored).
If a subsequent PLB 1-S-byte or byte or halfword burst read is contained in the prefetch
buffer, the data is returned to the PLB directly from the prefetch buffer, and no cycle is generated on
the
PCI.
If a PLB read to the PCI bridge occurs while the PCI bridge is prefetching and does not hit in the
prefetch buffer, then the PLB read is rearbitrated. After prefetching completes, any PLB read (of any
type
or address range) to the PCI bridge that does not hit in the prefetch buffer causes the prefetch
buffer to be emptied, and a new
PCI read to begin. PLB writes, including configuration writes, will
invalidate the prefetch buffer.
17.4.1.4 PLB Slave Write Handling
PLB master write requests are decoded into four types: PCI Memory (one of three PMM ranges), PCI
liD, PCI Configuration, or Special Cycles. If the request falls within any of these ranges, and is a
supported command type, the bridge claims the cycle by asserting a PLB wait signal.
If the write is
connected,
or translates to a PCI Configuration or Special Cycle, the bridge must gain access to the
PCI bus and successfully transfer the data before it may assert a PLB address acknowledge signal. If
the address is to PCI liD or memory, the bridge immediately asserts a PLB address acknowledge
signal and posts the write if there is sufficient buffer space.
17-12
PPC405GP User's Manual Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English