IBM PowerPC 405GP User Manual

Internal configuration writes are not allowed to execute if posted write data exists in either the PCI
slave
write buffer or the PLB slave write buffer. The internal configuration mechanism is described in
"PCI Bridge Configuration Registers" on page 17-19.
PLB Slave Write Post Buffer
The PCI bridge has a 32-byte write post buffer that may contain four separate single-beat PLB write
transactions
or one burst. New PLB write requests are rearbitrated if there is not enough room in the
write post buffer.
The buffers are not snooped, and are
always completed on the PCI bus in the same order as they are
received on the
PLB bus.
Each write buffer entry preserves the master
ID and drives the appropriate PLB bus busy signal until
the write is deallocated (it completes on the PCI bus). It is recommended that PLB masters do not use
PLB bus busy signal. Instead, PLB masters generating cycles to the PCI should use the standard PCI
mechanisms for data coherency.
17.4.1.5 Aborted PLB Requests
The PCI bridge aborts PLB reads only.
A PLB master accessing the PCI bridge can abort PLB write cycles only under the following
conditions:
• The PCI bridge rearbitrates the cycle.
•
The PCI bridge does not see the cycle because the PLB bus is granted to some other master. A
CPU/System Memory interface is expected to do this when a CPU cycle is pending to PCI bridge,
but a
PLB Master requests system memory access requiring snooping.
Note: If a PLB master aborts the write cycle at any other time, the results are undefined and the
bus may hang.
17.4.1.6 Retried PCI Reads
The PCI specification requires that a PCI master must repeat any read that is retried. The PCI bridge
adheres to this requirement.
It is only mentioned here because, under certain conditions with respect
to aborted
PLB reads, the PCI bridge must execute a PCI read and discard the data.
17.4.2 PCI-to-PLB Transaction Handling
This section describes how PCI bridge handles read and write requests from a PCI master device.
PCI bridge responds as a PCI target to PCI memory transactions when the PCI address is in one of
the two
PTM ranges and PCICO_CMD[MA] = 1. PCI bridge responds by claiming the PCI cycle and
mastering a
cycle on the PLB.
Preliminary PCI Interface 17-13

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English