IBM PowerPC 405GP

10.5.2 UIC Enable Register (UICO_ER)
The fields of the UICO_ER, which correspond to the fields of the UICO_SR, enable or disable the
reporting of the corresponding
fields of the UICO_SR.
If
a UICO_ER field is set to 1, the corresponding field of the UICO_SR generates a critical or non-
critical
interrupt signal to the processor core, if the UICO_SR field is set to 1. If a UICO_ER field is set
to
0, the corresponding field of the UICO_SR does not generate a critical or non-critical interrupt
signal to the processor core, regardless of the setting of the UICO_SR field. The critical and non-
critical
interrupt signals in the processor core are controlled by fields in the Machine State Register
(MSR).
The
class of generated signals (critical or non-critical) is controlled by the UICO_CR.
UOIE IICIE PCIIE D11E D31E MSIE MREIE MRDIE EPSIE PPMIE
EIR1 E EIR3E EIR5E
U11E EMIE DOlE D21E EWIE MTEIE MTDIE ENIE ECIE
EIROE EIR2E EIR4E EIR6E
Figure 10-2. UIC Enable Register (UICO_ER)
0
UOIE UARTO Interrupt Enable
o UARTO interrupt is disabled.
1 UARTO interrupt is enabled.
1 U11E UART1 Interrupt Enable
o UART1 interrupt is disabled.
1 UART1 interrupt is enabled.
2 IICIE IIC Interrupt Enable
o IIC interrupt is disabled.
1 IIC interrupt is enabled.
3
EMIE External Master Interrupt Enable
100 External
master interrupt is disabled.
1 OxxExternal master interrupt is enabled.
4 PCIIE PCI Interrupt Enable
o PCI interrupt is disabled.
1 PCI interrupt is enabled.
5
DOlE DMA Channel 0 Interrupt Enable
o DMA channel 0 interrupt is disabled.
1 DMA channel 0 interrupt is enabled.
6
D11E DMA Channel 1 Interrupt Enable
o DMA channel 1 interrupt is disabled.
1 DMA channel 1 interrupt is enabled.
7 D21E DMA Channel 2 Interrupt Enable
o DMA channel 2 interrupt is disabled.
1 DMA channel 2 interrupt is enabled.
10-6 PPC405GP User's Manual
Preliminary