IBM PowerPC 405GP User Manual

After any program interrupt, the contents of the MSR are written into SRR1 and the MSR bits are
written with the
values shown in Table 10-16. The high-order 16 bits of the program counter are
written with the contents of the EVPR; the
low-order 16 bits of the program counter are written with
Ox0700. Interrupt processing begins at the new address in the program counter.
Executing an
rfi instruction restores the program counter from SRRO and the MSR from SRR1, and
execution resumes at the address
in the program counter.
Table 10-16.
Register Settings during Program Interrupts
SRRO Written with the address of the excepting instruction
SRR1 Written with the contents of the MSR
MSR
WE, EE, PR, DWE, IR, DR ~ 0
CE, ME, DE ~ unchanged
PC
EVPR[0:15]II Ox0700
ESR
Written with the type of program interrupt. (See Table 10-15)
MCI
~ unchanged
All other bits are cleared.
10.19 System Call Interrupt
System call interrupts occur when a sc instruction is executed. The PPC405GP writes the address of
the instruction
following the sc into SRRO. The contents of the MSR are written into SRR1 and the
MSR bits are written with the
values shown in Table 10-17. The high-order 16 bits of the program
counter are then written with the contents of the EVPR and the
low-order 16 bits of the program
counter are written with
OxOCOO. Interrupt processing begins at the new address in the program
counter.
Executing an
rfi instruction. restores the program counter from SRRO and the MSR from SRR1 , and
execution resumes at the address
in the program counter.
Table 10-17.
Register Settings during System Call Interrupts
SRRO
Written with the address of the instruction following the sc instruction
SRR1
Written
with the contents of the MSR
MSR
AP, APE, WE, EE, PR, DWE, IR, DR ~ 0
CE, ME, DE ~ unchanged
PC EVPR[0:15]II OxOCOO
10.20 Programmable Interval Timer (PIT) Interrupt
For a discussion of the PPC405GP timer facilities, see Chapter 11, "Timer Facilities:' The PIT is
described in
"Programmable Interval Timer (PIT)" on page 11-4.
If the PIT interrupt is enabled by TCR[PIE] and MSR[EE], the PPC405GP initiates a PIT interrupt after
detecting a time-out from the
PIT. Time-out is detected when, at the beginning of a clock cycle,
TSR[PIS]
= 1. (This occurs on the cycle after the PIT decrements on a PIT count of 1.) The
PPC405GP immediately takes the interrupt. The address of the next sequential instruction is saved in
SRRO; simultaneously, the contents of the MSR are written into SRR1 and the MSR is written with the
values shown in Table 10-18. The high-order 16 bits of the program counter are then written with the
Preliminary Interrupt Controller Operations
10-41

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English