IBM PowerPC 405GP User Manual

1
0
3
1
1
Figure 3-3. Count Register (CTR)
0:31 Count
Used as count for branch conditional with
decrement instructions, or as address for
branch-to-counter instructions.
3.3.2.2 Link Register (LR)
The LR is written from a GPR using mtspr, and by branch instructions that have the LK bit set to 1.
Such branch instructions load the LR with the address of the instruction following the branch
instruction. Thus, the LR contents can be used as the return address for a subroutine that was called
using the branch.
The LR contents can
be used as a target address for the bclr instruction. This allows branching to any
address.
When the
LR contents represent an instruction address, LR
30
:
31
are assumed to be 0, because all
instructions must be word-aligned. However, when LR is read using mfspr, all 32 bits are returned as
written.
The LR is
in the user programming model.
1
0
Figure 3-4. Link Register (LR)
Link Register contents
3.3.2.3 Fixed Point Exception Register (XER)
If (LR) represents an instruction address,
LR
30
:
31
should be o.
The XER records overflow and carry conditions generated by integer arithmetic instructions.
The
Summary Overflow (SO) field is set to 1 when instructions cause the Overflow (OV) field to be set
to 1 . The
SO field does not necessarily indicate that an overflow occurred on the most recent
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PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English