accesses hit
in
the ITLB, the address translation mechanisms
in
the UTLB are available for use by
data accesses
simultaneously.
The ITLB requests a new entry from the UTLB when an ITLB miss occurs. A four-cycle latency occurs
at each
ITLB miss that is also a UTLB hit; the latency is longer if it is also a UTLB miss,
or
if there is
contention for the UTLB from the data side.
A round-robin replacement algorithm replaces existing
entries with new entries.
6.3.4 Shadow Data TLB
To
enhance performance, eight data-side TLB entries are kept in a eight-entry fully-associative
shadow array. This array, called the data TLB (DTLB), helps to avoid TLB contention between
instruction accesses to the TLB and
load/store operations. Replacement and invalidation of the DTLB
entries is managed by hardware.
See "Shadow TLB Consistency" on page 6-8 for details.
The DTLB can be considered a level-1 data-side TLB; the UTLB serves as the level-2 data-side TLB.
The DTLB is used
only by instructions
in
execute for storing data address translations. Each DTLB
entry contains the
translation information for a page. The processor uses the DTLB for address
translation of data accesses when MSR[DR] =
1.
6.3.4.1
DTLB
Accesses
The execute unit accesses the DTLB independently of the rest of the MMU. DTLB accesses are
transparent to the executing program, except that DTLB hits contribute to higher
overall instruction
throughput by
allowing instruction address translations to occur in parallel. Therefore, when data
accesses hit in the DTLB, the address
translation mechanisms in the UTLB are available for use by
instruction accesses
simultaneously.
The DTLB requests a new entry from the UTLB when a DTLB miss occurs. A three-cycle latency
occurs at each DTLB miss that is also a UTLB hit; the latency is longer if it is also a UTLB miss.
If
there is contention for the UTLB from the instruction side, the data side has priority. A round-robin
replacement algorithm replaces existing entries with new entries.
Preliminary Memory Management 6-7
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