17.5.3.23
PCllnterrupt
Control/Status Register (PCICO_ICS)
A PLB master or a PCI master device may generate an interrupt to the PCI bus by writing a 1 to bit
O.
Clearing this bit clears the interrupt. Bit 0 also reports the status of the interrupt. A value of 1 means
that the interrupt is asserted, a
value of 0 means that the interrupt is deasserted.
1
I 0 I
Figure 17-44.
PCllnterrupt
Control/Status Register
7:1
.:
Reserved
These bits return
0 when read.
0
API
Asset
PCI
interrupt
When software sets this bit, the
PCI
bridge
asserts its Interrupt pin.
17.5.3.24 Error Enable Register (PCICO_ERREN)
ERREN enables detection and reporting of various errors for the PCI bridge (see "Error Handling" on
page 17-55).
7
6
17-42
I.>
.:
...
...
•
...•..
TAEE
TAEE
MEDE
WDPE
t t t
1716154131211101
f t f
MERE
MEAE MAEE
Figure 17-45. Error Enable Register (PCICO_ERREN)
Reserved
Target Abort Error Enable
While the
PCI bridge
is
the
PCI
master,
o Disabled
this bit enables the detection of a target
1 Enabled
abort as
an
error condition. If
TAEE
is
enabled, the
PCI bridge reports PLB bus
errors.
PPC405GP User's Manual Preliminary
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