5. Modify the value
in
OCMO_DSARC.
6. Set OCMO_DSCNTL[DSEN] = 1 to enable data-side OCM accesses.
OCMO_DSCNTL[DOF] should remain at its reset value of
1.
See "OCM Data-Side Control Register
(OCMO_DSCNTL)" on page 5-7 for details.
8.9.2 UIC Initialization
The following information does not provide all initialization information for the UIC. Some initialization
details are application-dependent.
The polarity and sensitivity of the on-chip interrupts must be initialized for proper chip operation. The
fields controlling on-chip interrupts in the
UIC Polarity Register (UICO_PR
o
:
1S
) must be set to 1. See
"UIC
Polarity Register (UICO_PR)" on page 10-10 for details. The fields controlling on-chip interrupts
in
the UIC Trigger Register (UICO_
TRo:2
and UICO_ TR
4
:
1S
) must be set to 0. The field controlling the
external master interrupt trigger
(UICO_ TR
3
)
must be set to
1.
See "UIC Trigger Register (UICO_ TR)"
on page 1 0-13 for details.
8.9.3 UART Initialization
Bits 19 and 20 of Chip Control Register ° (CPCO_CRO) control which of two modem control signal
pairs, Data
Set Ready (DSR) and Data Terminal Ready (DTR)
or
Clear to Send (CTS) and Ready to
Send (RSR), are used. The signal pairs are implemented using the multiplexed pins
UART1_DSR[UART1_CTS], controlled
by
CPCO_CR0
19
, and UART1_RTS[UART1_DTR], controlled
by
CPCO_CR0
20
. After reset, CPCO_CR0
19
or CPCO_CR0
20
must be changed to achieve a required
typical pairing.
8.10 PPC405GP Initial Processor Sequencing
After any reset, the processor core fetches the word at address OxFFFFFFFC and attempts to
execute it. Because the only memory configured immediately after reset is the upper 2MB region
(OxFFEOOOOO-OxFFFFFFFF), the instruction at OxFFFFFFFC must be a branch instruction.
Because the processor is initially in big endian mode, initialization code must be
in
big endian format
until the end ian storage attribute for the addressed region is changed,
or
until code branches to a
region defined as little end ian storage.
Before a reset operation begins, the system must provide non-volatile memory, or memory initialized
by some mechanism external to the processor. This memory must be located at address
OxFFFFFFFC in the upper 2MB region. This memory can be attached to the external bus controller
(EBC)
or
to the system PCI bus. For memory attached to the EBC, the upper 2MB bank configuration
after reset is 256 wait states, three cycles of address to chip select delay, three cycles of chip select to
output enable delay, and seven cycles of hold time. The bus width (8-, 16-, or 32-bit) is controlled by
the
ROM width strapping signals. See "Pin Strapping" on page
9-1
for details. See "Local Processor
Boot from
PCI Memory"
on
page 17-64 for information about memory attached to the system PCI
bus.
8-14
PPC405GP User's Manual Preliminary
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