The eieio instruction guarantees the order of storage accesses. All storage accesses that precede
eieio
complete before any storage accesses that follow the instruction, as
in
the following example:
stb X Store to peripheral, address
X;
this resets a status bit
in
the device
eieio Guarantee
stb
X completes before next instruction
Ibz Y Load from peripheral, address
Y;
this is the status register updated by
stb
X.
eieio
was necessary, because the read and write addresses are different, but
affect each other
The PPC405GP
implements both
sync
and
eieio
identically,
in
the manner described above for
sync.
In
the PowerPC Architecture,
sync
can function across all processors in a multiprocessor
environment;
eieio
functions only within its executing processor. The PPC405GP does not provide
hardware support for
multiprocessor memory coherency, so
sync
does not guarantee memory
ordering across
multiple processors.
3.11
Instruction Set
The PPC405GP instruction set contains instructions defined
in
the PowerPC Architecture and
instructions specific to the
IBM PowerPC 400 family of embedded processors.
Chapter 24,
"Instruction Set," contains detailed descriptions of each instruction.
Appendix
A,
"Instruction Summary," alphabetically lists each instruction and extended mnemonic and
provides a short-form description. Appendix
B,
"Instructions by Category," provides short-form
descriptions of instructions, grouped by the instruction categories
listed
in
Table 3-21, "PPC405GP
Instruction Set
Summary:' on page 3-47.
Table
3-21
summarizes the PPC405GP instruction set functions by categories. Instructions within
each category are described
in
subsequent sections.
Table 3-21. PPC405GP
Instruction
Set
Summary
Storage Reference load, store
Arithmetic
add, subtract, negate, multiply, multiply-accumulate, multiply halfword, divide
Logical
and, andc,
or,
orc, xor, nand, nor, xnor, sign extension, count leading zeros
Comparison compare, compare log.ical, compare immediate
Branch branch, branch conditional, branch to LR, branch to CTR
CR Logical
crand, crandc, cror, crorc, crnand, crnor, crxor, crxnor, move CR field
Rotate rotate and insert, rotate and mask, shift left, shift right
Shift shift left, shift right, shift right algebraic
Cache Management invalidate, touch, zero, flush, store, read
Interrupt Control
write to external interrupt enable bit, move to/from
MSR, return from interrupt,
return from critical interrupt
Processor Management system call, synchronize, trap, move to/from DCRs, move to/from
SPRs, move
to/from CR
Preliminary
Programming Model
3-47
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