IBM PowerPC 405GP User Manual

interrupt occurs upon attempted execution and the cache line is invalidated. If any word in the line is
in error, the cache
line is invalidated after the line fill.
ESR[MCI]
is set, even if MSR[ME] = O. This means that if a machine check-instruction interrupt
occurs while running
in code in which MSR[ME] is disabled, the machine check-instruction interrupt
is recorded
in the ESR, but no interrupt occurs. Software running with MSR[ME] disabled can sample
ESR[MCI]
to determine whether at least one machine check-instruction interrupt occurred during
the disabled execution.
If a new machine check-instruction interrupt occurs after MSR[ME] is enabled again, the new
machine
check-instruction interrupt is recorded in ESR[MCI] and the machine check-instruction
interrupt handler is invoked. However, enabling MSR[ME] again does not cause a machine Check
interrupt to occur
simply due to the presence of ESR[MCI] indicating that a machine check-
instruction interrupt occurred while MSR[ME] was disabled. The machine check-instruction interrupt
must occur
while MSR[ME] is enabled for the machine check interrupt to be taken. Software should,
in general, clear the ESR bits before returning from a machine check interrupt to avoid any ambiguity
when handling subsequent machine check interrupts.
Table 10-8. Register Settings during Machine Check-Instruction Interrupts
SRR2
Written with the address that caused the machine check.
SRR3 Written with the contents of the MSR
MSR
WE, CE, EE, PR, ME, OWE, DE,IR, DR~O
PC EVPR[O:15] II Ox0200
ESR
MCI~1
All other bits are cleared.
10.13.2 Data Machine Check Handling
When a machine check occurs on an data access, a machine check-data interrupt occurs. To
determine the cause of a machine check, examine the various error reporting registers of the external
PLB
slaves.
Table 10-9. Register Settings during Machine Check-Data Interrupts
SRR2 Written with the address of the next sequential instruction.
SRR3
Written with the contents of the MSR
MSR
WE, CE, EE, PR, ME, OWE, DE, IR, DR~O
PC
EVPR[O:15]
II Ox0200
10.14 Data Storage Interrupt
The data storage interrupt occurs when the desired access to the effective address is not permitted
for any of the
following reasons:
• A UO fault: any store to an EA with the UO storage attribute set and CCRO[UOXE] = 1
10-36
PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English