3.4.3 Summary of Instructions Causing Alignment Exceptions
Table 3-16 summarizes the instructions that cause alignment exceptions and the conditions under
which the
alignment exceptions occur.
Table 3-16. Alignment Exception Summary
Instructions
CausIng
Alignment
Exceptions
Conditions
dcbz
EA
in
non-cachable or write-through storage
dcread, Iwarx,
stwcx.
EA
not word-aligned
3.5 Byte Ordering
The following discussion describes the "endianness" of the PPC405GP core, which, by default and
in
normal use is "big endian." The PPC405GP also contains "little end ian" peripherals and supports the
attachment of
external little end ian peripherals.
If scalars (individual data items and instructions) were indivisible, "byte ordering" would not be a
concern.
It is meaningless to consider the order of bits or groups of bits within a byte, the smallest
addressable
unit of storage; nothing can be observed about such order. Only when scalars, which the
programmer and processor regard as
indivisible quantities, can comprise more than one addressable
unit of storage does the question of byte order arise.
For a machine
in
which the smallest addressable unit of storage is the 32-bit word, there is no
question of the ordering of bytes within words.
All transfers of individual scalars between registers and
storage are of words, and the address of the byte containing the high-order eight bits of a
scalar is the
same as the address of any other byte of the
scalar.
For the PowerPC Architecture, as for most computer architectures currently implemented, the
smallest addressable unit of storage is the a-bit byte. Other scalars are halfwords, words, or
doublewords, which consist of groups of bytes. When a
word-length scalar is moved from a register to
storage, the
scalar is stored in four consecutive byte addresses. It thus becomes meaningful to
discuss the order of the byte addresses with respect to the
value of the scalar: that is, which byte
contains the highest-order eight bits of the
scalar, which byte contains the next-highest-order eight
bits, and so on.
Given a
scalar that contains multiple bytes, the choice of byte ordering is essentially arbitrary. There
are
4!
= 24 ways to specify the ordering of four bytes within a word, but only two of these orderings
are
commonly used:
• The ordering that assigns the lowest address to the highest-order ("leftmost") eight bits of the
scalar, the next sequential address to the next-highest-order eight bits, and so on.
This ordering is
called big endian because the "big end" of the scalar, considered as a binary
number,
comes first
in
storage.
• The ordering that assigns the lowest address to the lowest-order ("rightmost") eight bits of the
scalar, the next sequential address to the next-lowest-order eight bits, and so on.
This ordering is
called little endian because the "little end" of the scalar, considered as a binary
number, comes first
in
storage.
3-28
PPC405GP User's Manual Preliminary
To Next Page
Loading...
Need help?
General
