The following status bits are set:
1.
PCICO_STATUS[DEPE] = 1 if the bridge PCI master detects bad parity on read data, regardless of
the state of
PCIO_CMD[PER]. Writing a 1 to PCICO_STATUS[DEPE] clears the field.
2.
If a data bus parity error is detected as an error, PCICO_ERRSTS[MEAE] = 1 to indicate an event
that
would cause a PLB bus error signal to be asserted by the bridge PLB slave, regardless of the
state of
PCICO_ERREN[MEAE]. Writing a 1 to PCICO_ERRSTS[MEAE] = 1 clears the field.
3.
PCICO_PLBBEAR and the PCICO_PLBBESRx are updated as follows:
The address of the PCI transaction where parity errors occurred is saved
in
the.
PCICO_PLBBEAR.
PCICO_PLBBEAR
is set if all PCICO_PLBBESRx[MxAL] = 1 (PCICO_PLBBEAR is unlocked). If
PCICO_PLBBESRx[MxFL]
=
1,
PCICO_PLBBESRx[MxET] =
Ob001
to indicate a parity error, and
PCICO_PLBBESRx[MxRWS] is set to ° on a write, 1 on a read. If PCIO_CMD[PER] = °
or
PCICO_ERRSTS[MEAE] =
0,
no PCICO_PLBBEAR
or
PCICO_PLBBESRx update is performed.
Note:
For clock ratios greater than
2:1
(independent of asynchronous/synchronous mode), the PCI
bridge detects errors but does not assert a PLB bus error signal
or
log the error
in
PCICO_PLBBEAR, PCICO_PLBBESRx, and PCICO_ERRSTS[MEAE].
17.6.6 PCI Address Bus Parity Error While PCI Target
This error occurs when a PCI address bus parity error is detected during the address phase of a cycle
in
which the bridge is the PCI target. PCI uses even parity.
Setting PCICO_CMD[PER] = ° masks this error. This error does not have an explicit status bit,
however the
following actions are taken:
1.
PCICO_STATUS[SSE] = 1 to indicate assertion of PCISErr, if the mask at PCICO_CMD[SE] =
1.
Writing a 1 to PCICO_STATUS[SSE] clears the field.
2.
PCICO_STATUS[DEPE] = 1 to indicate a PCI bus parity error, regardless of the state of
PCIO_CMD[PER]. PCICO_STATUS[DEPE] = 1 when any type of PCI parity error is detected.
Writing a 1 to
PCICO_STATUS[DEPE] clears the field.
17.6.7 PLB Master
Bus
Error Detection
This error occurs when the bridge PLB master detects a PLB bus error. If the bridge PLB master
receives a PLB bus error
while mastering a read, the master associates the error with the currently
executing read.
If the master receives a PLB bus error while mastering a write or while idle, the
master associates the error with a write.
PLB bus error detection is masked by
PCICO_ERREN[MEDE] =
0.
If PCICO_ERREN[MEDE] =
1,
PLB bus error detection is enabled.
PCICO_ERREN[MEREJ controls
the response of the bridge PCI target to PLB bus error detection. If
PCICO_ERREN[MERE]
= 10 or 11, the bridge PCI target will execute a target abort. If
PCICO_ERREN[MERE]
=
01
or
11, the bridge PCI target asserts PCISErr and allows the transaction
to continue.
If PCICO_ERREN[MERE] = 11, the bridge PCI target both target aborts and asserts
PCISErr.
17-58
PPC405GP User's Manual
Preliminary
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