IBM PowerPC 405GP User Manual

4.2.5 DCU Coherency
The DCU does not provide snooping. Application programs must carefully use cache-inhibited
regions and cache
control instructions to ensure proper operation of the cache in systems where
external devices can update memory.
4.3 Cache Instructions
For detailed descriptions of the instructions described in the following sections, see Chapter 24,
"Instruction Set."
In
the instruction descriptions, the term "block" is synonymous with cache line. A block is the unit of
storage operated on by
all cache block instructions.
4.3.1 ICU Instructions
The following instructions control instruction cache operations:
icbi
icbt
Instruction Cache Block Invalidate
Invalidates
a cache block.
Instruction
Cache Block Touch
Initiates a block fill, enabling a program to begin a cache block fetch b.efore the
program needs an instruction in the
block.
The program can subsequently branch to the instruction address and fetch the
instruction without incurring a cache miss.
This is a
privileged instruction.
iccci Instruction Cache Congruence Class Invalidate
icread
Invalidates the instruction cache array.
This is a
privileged instruction.
Instruction Cache Read
Reads either an instruction cache tag entry
or an instruction word from an
instruction cache
line, typically for debugging. Fields in CCRD control instruction
behavior (see
"Cache Control and Debugging Features" on page 4-11).
This is a
privileged instruction.
Preliminary
Cache Operations
4-9

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English