The PowerPC instruction set and Special Purpose Registers (SPRs) provide a high degree of user
control over configuration and operation of the processor core functional units.
1.5.1 Data Types
Processor core operands are bytes, halfwords, and words. Multiple words
or
strings of bytes can be
transferred using the load/store multiple and load/store string instructions. Data is represented
in
twos
complement notation
or
in
unsigned fixed-point format.
The address of a multibyte operand is always the lowest memory address occupied by that operand.
Byte ordering can be selected as big end ian (the lowest memory address of an operand contains its
most significant byte)
or
as little endian (the lowest memory address of an operand contains its least
significant byte).
See "Byte Ordering" on page 3-28 for more information about big and little end ian
operation.
1.5.2 Processor Core Register Set Summary
The processor core registers can be grouped into basic categories based on function and access
mode: general purpose registers (GPRs), special purpose registers (SPRs), the machine state
register (MSR), the condition register (CR), and device control registers (DCRs).
Chapter 25,
"Register Summary," provides a register diagram and a register field description table for
each register.
1.5.2.1
General Purpose Registers
The processor core contains 32 GPRs; each register contains 32 bits. The contents
of
the GPRs can
be transferred from memory using load instructions and stored to memory using store instructions.
GPRs, which are specified as operands in many instructions, can also receive instruction results and
the contents of other registers.
1.5.2.2 Special Purpose Registers
Special Purpose Registers (SPRs), which are part of the PowerPC Architecture, are accessed using
the mtspr and mfspr instructions. SPRs control the use of the debug facilities, timers, interrupts,
storage control attributes, and other architected processor resources.
All SPRs are privileged (unavailable to user-mode programs), except the Count Register (CTR), the
Link Register (LR),
SPR General Purpose Registers (SPRG4-SPRG7, read-only), and the Fixed-
poi,nt Exception Register (XER). Note that access to the Time Base Lower (TBL) and Time Base
Upper (TBU) registers, when addressed as SPRs, is write-only and privileged. However, when
addressed as Time Base Registers (TBRs), read access to these registers is not privileged.
See
"Time
Base Registers" on page 25-3 for more information.
1.5.2.3 Machine State Register
The processor core contains a 32-bit Machine State Register (MSR). The contents of a GPR can be
written to the
MSR using the mtmsr instruction, and the MSR contents can be read into a GPR using
the mfmsr instruction. The
MSR contains fields that control the operation of the processor core.
1-10 PPC405GP User's Manual
Preliminary
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