In
practice, cache synonyms occur when a real instruction page having multiple virtual mappings
exists
in
multiple cache lines. For 1 KB pages, all EAs differing
in
EA
19
:
21
must be cast out of cache,
using an
icbi
instruction for each such EA (up to 8 per cache line
in
the page). For 4KB pages, all EAs
differing in EA
19
must be cast out
in
the same manner (up to 2 per cache line in the page). For larger
pages, cache synonyms do not occur, and casting out any of the multiple EAs removes the physical
information from the cache.
Programming
Note:
To
prevent the occurrence of cache synonyms, use only page sizes greater
than the cache way size (8KB), if
possible. For the PPC405GP, the minimum such page size is
16KB.
4.1.4 ICU Coherency
The ICU does not "snoop" external memory
or
the DCU. Programmers must follow special procedures
for
ICU synchronization when self-modifying code is used or if a peripheral device updates memory
containing instructions.
The
following code example illustrates the necessary steps for self-modifying code. This example
assumes that addr1 is both data and instruction cachable.
stw
dcbst
sync
icbi
isync
regN, addr1
addr1
addr1
# the data
in
regN is to
be~ome
an instruction at addr1
# forces data from the data cache to memory
# wait until the data actually reaches the memory
# the previous value at addr1 might already be
in
the instruction cache; invalidate it
in
the cache
# the previous value at addr1 may already have been
pre-fetched into the queue;
invalidate the queue
so that the instruction must be re-fetched
4.2 DCU Organization
The DCU manages data transfers between external cachable memory and the general-purpose
registers
in
the execution unit.
The DCU contains a two-way set-associative 8KB 1
KB
cache memory. Each way is organized in 128
lines of eight words (32 bytes) each.
Preliminary Cache Operations
4-5
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