Table 10-3. Interrupt Handling Priorities (continued)
Critical
or
Priority Interrupt Type
Noncritical
Causing Conditions
16 External interrupt input Noncritical Interrupts
from
the
external interrupt (external
to
the
processor
core)
input
17
Fixed
Interval Timer
(FIT)
Noncritical
Posting
of
an
enabled
FIT
interrupt
in
the
TSR
18
Programmable Interval
Noncritical
Posting
of
an
enabled
PIT
interrupt
in
the
TSR
Timer
(PIT)
10.10 Critical and Noncritical Interrupts
The PPC405GP processes interrupts as noncritical and critical. Twelve interrupts are defined as
noncritical: data storage, instruction storage, an active external interrupt input, alignment, program,
system
call, programmable interval timer (PIT), fixed interval timer (FIT), data TLB miss, and
instruction
TLB
miss. Five interrupts are defined as critical: machine check interrupts (instruction- and
data-side), debug interrupts (any
of
the seven types), interrupts caused by an active critical interrupt
input, and the first time-out from the watchdog timer.
When a
noncritical interrupt is taken, Save/Restore Register 0 (SRRO) is written with the address of
the excepting instruction (most synchronous interrupts) or the next sequential instruction to be
processed (asynchronous interrupts and system
call).
If
the PPC405GP was executing a multicycle instruction (multiply, divide, or cache operation), the
instruction is terminated and its address is written in
SRRO.
Aligned scalar
loads/stores that are interrupted
do
not appear on the PLB. An aligned scalar
load/store cannot be interrupted after it is requested on the PLB, so the Guarded (G) storage attribute
does not need to prevent the interruption of an
aligned scalar load/store.
To
enhance performance, the DCU can respond to non-cachable load requests by retrieving a line
instead of a word. This is controlled by CCRO[LWL]. Note, however, that If CCRO[LWL] = 1, and the
target non-cachable region is
also marked as guarded (the G storage attribute is set to 1), that the
DCU
will request on the PLB only those bytes requested by the CPU.
Load/store
multiples, load/store string, and misaligned scalar loads/stores that cross a word boundary
can be interrupted and restarted upon return from the interrupt
handler.
When load instructions terminate, the addressing registers are not updated. This ensures that the
instructions can be restarted; if the addressing registers were in the range of registers to be loaded,
this
would be an invalid form in any event. Some target registers of a load instruction may have been
written by the time of the interrupt; when the instruction restarts, the registers will
simply be written
again. Similarly, some of the target memory of a store instruction may have been written, and is
written again when the instruction restarts.
Save/Restore Register 1 (SRR1) is written with the contents of the MSR; the MSR is then updated to
reflect the new machine context. The new MSR contents take effect beginning with the first instruction
of the interrupt
handling routine.
Interrupt handling routine instructions are fetched at an address determined by the interrupt type. The
address of the interrupt
handling routine is formed by concatenating the 16 high-order bits
of
the
10-26
PPC405GP User's
Manual
Preliminary
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