IBM PowerPC 405GP

Chapter 1. Overview
The IBM PowerPC 405GP 32-bit reduced instruction set computer (RISC) embedded processor,
referred to as the PPC405GP, is a system-on-a-chip
(SOC) that integrates a PowerPC embedded
processor core with a rich set of on-chip peripherals:
• SDRAM controller
• External
bus controller (EBC)
• PCI bus interface
• Direct memory access (DMA) with scatter/gather support
• Ethernet and media access layer (MAL) interfaces
• Two serial ports
• Inter-integrated circuit (IIC) interface
• General-purpose input/output (GPIO)
In addition, the PPC405GP supports CodePack™, a code compression scheme that can significantly
reduce
application code memory requirements, and a variety of debug tools.
This chapter describes:
• PPC405GP features
• The PowerPC Architecture™
• The PPC405GP implementation of the IBM PowerPC Embedded Environment, an extension of the
PowerPC Architecture for embedded
applications
• PPC405GP
organization, including a block diagram and descriptions of the functional units
• PPC405GP registers
• PPC405GP addressing modes
Preliminary Overview 1-1