table must be word-aligned.
If
the source, destination and scatter/gather address registers are not
appropriately aligned an error. occurs immediately after the channel is enabled.
Table 18-4. Address Alignment Requirements
Required
Alignment
for:
DMAO_CRn[PW]
Source
Address
Register
(DMAO_SAn)
Setting
and
Destination
Address
(DMAO_DAn)
ObOO
Byte (8-bit)
Ob01
Halfword (16-bit)
Ob10
Word (32-bit)
Ob11
Doubleword (64-bit)
18.6.2 PLB Timeout
The DMA controller uses PLB operations to read and write memory. A PLB timeout results if the DMA
controller attempts to access a non-existent memory location. This will occur if the source, destination
or scatter/gather address registers do not map to
valid memory locations.
18.6.3 Slave Errors
If the DMA controller detects an error from a PLB slave, it finishes any active read/write pair transfer
on the
channel and then reports an error.
An
SDRAM uncorrectable ECC error and an EBC bank
protection error are
examples of PLB slave errors.
18.7 DMA Interrupts
Each DMA channel can generate interrupts for end of transfer, terminal count and error conditions.
Interrupts from a particular DMA channel are enabled by setting the channel enable bit
in
the
channel's control register (DMAO_CRn[CIE]=1). When an interrupt occurs for a given channel, the
DMA
controller sends a signal to the Universal Interrupt Controller. For the PPC405GP's CPU to take
an exception, interrupts from the
particular DMA channel must be enabled in the interrupt controller's
interrupt enable register (UICO_ER). Also, the CPU's machine state register's interrupt enable bit
must be
enabled for the appropriate interrupt type (critical
or
non-critical), MSR[EE,CE]. See
Chapter
10, "Interrupt Controller Operations" for more information on interrupt controller processing.
For DMA
channels with interrupts enabled (DMAO_CRn[CIE]=1) and not performing a scatter/gather
transfer an interrupt is generated
while any of
the
following are true:
DMAO_CRn[TCE]=1 and DMAO_SR[CSn]=1
DMAO_SR[TSn]=1
DMAO_SR[Rln]=1
When a channel is performing a scatter/gather transfer, interrupt generation is further qualified by the
TCI, ETI and ERI bits loaded from the descriptor table (see Table 18-5, "Scatter/Gather Descriptor
Table:' on page 18-16). Any of the following conditions cause an interrupt during a scatter/gather
transfer when interrupts are
enabled for the channel (DMAO_CRn[CIE=1]):
Preliminary Direct Memory Access Controller
18-15
To Next Page
Loading...
Need help?
General
