M (memory coherent,1 bit)
For implementations that support multiprocessing, the M storage attribute improves the performance
of memory coherency management. Because the
PPC405GP does not provide mUlti-processor
support
or
hardware support for data coherency, the M bit is implemented, but has no effect.
G (guarded,1 bit)
When set (TLBLO[G]
= 1), indicates that the hardware cannot speculatively access the location for
pre-fetching
or
out-of-order load access. The G storage attribute is typically used to protect memory-
mapped
I/O from inadvertent access. Attempted execution of an instruction from a guarded data
storage address while instruction address
translation
is
enabled results
in
an instruction storage
interrupt because data storage and memory mapped
I/O (MMIO) addresses are not used to contain
instructions.
An instruction fetch from a guarded region does not occur until the execution
pipeline is empty, thus
guaranteeing that the access is necessary and therefore not
speculative. For this reason,
performance is degraded when executing out of guarded regions, and software
should avoid
unnecessarily marking regions of instruction storage as guarded.
In real mode, the Storage Guarded Register (SGR) controls guarding.
UO
(user-defined attribute, 1 bit)
When set
(TLBLO[UO] = 1), indicates the user-defined attribute applies to the data
in
the associated
page. This storage attribute
controls Code Pack decompression for a page.
In real mode, the Storage User-defined 0 Register (SUOR) controls the setting of the
UO
storage
. attribute.
E (endian, 1 bit)
When set (TLBLO[E]
= 1), indicates that data
in
the associated page is stored in true little end ian
format.
In real mode, the Storage Little-Endian Register (SLER) controls the setting of the E storage attribute.
6.3.3 Shadow Instruction TLB
To
enhance performance, four instruction-side TLB entries are kept
in
a four-entry fully-associative
shadow array. This array, called the instruction TLB (ITLB), helps to avoid TLB contention between
instruction accesses to the TLB and Joad/store operations.
Replacement and invalidation of the ITLB
entries is managed by hardware (see "Shadow TLB Consistency" on page 6-8 for details).
The ITLB can be considered a level-1 instruction-side TLB; the UTLB serves as the level-2'
instruction~side
TLB. The ITLB is used only by instruction fetches for storing instruction address
translations. Each ITLB entry contains the translation information for a page. The processor uses the
ITLB for address translation of instruction accesses when MSR[IR] = 1.
6.3.3.1
ITLB Accesses
The instruction unit accesses the ITLB independently of the rest of the MMU. ITLB accesses are
transparent to the executing program, except that
ITLB hits contribute to higher.overall instruction
throughput by
allowing data address translations to occur
in
parallel. Therefore, when instruction
6-6
PPC405GP User's Manual
Preliminary
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