EOTn[TCn] should be immediately deasserted to prevent the subsequent transfer from ending
prematurely. Figure 18-12 on page 18-19 shows the required timing. .
Cycle I 1 I 2 I 3 I
~
to to tt=n to to to tt=n
~~I---,_
PerClk
ru1JLJ)
U)
U)
U"U)
U)
U)
U)
U"U)}SlfL
DMAReqn
--i.J
DMAAckn
~----------~~~----~~~~------~
, pSC'
pwc
PHC
psc:
pwa
i PHC'
~~~~
__
~
____
~~~
__
~
________
~~r:J'7\~'
I
~~i
_.
__
~
EOTn[TCnj
PerDataO:31
PerParO:3
i
PerRfW
:--~~:--:--->--'----'
__
~-I-C\:--'>""-:--:--:--
__
""'t-=.
__
.
___
,'
;
'PerDE
,...._--~-:---I
CJ
FferWE
,...._----,...._-J
,'---.)
CJ
'PerWBEO:3
1
dO
CJ
'PerCSO:7
_~
___
:---II
CJ
PerBLast
I
PerAddrO:31
PerReady
_~~
__
:--:--:--_:--:--:--
_______
:--:--~--:--
__
Figure 18-12. Memory to Peripheral DMA Transfer
For both peripheral-to-memory and memory-to-peripheral transfers the transfer width
(DMAO_CR[PW]) must be set to the data bus width of the peripheral. This is because the DMA
controller does not pack
or
unpack data on the peripheral side of transaction.
Peripheral-to-Memory Transfer
To
perform a peripheral-to-memory DMA transfer from an ESC-attached DMA peripheral:
1.
Set destination address register (DMAO_DAn) to the desired memory location. The address must
be
aligned to the programmed transfer width (DMAO_CRn[PW]), otherwise an alignment error will
occur.
2.
Program the count register (DMAO_CTn) for the number of transfers.
3.
Clear the channel's status bits in the DMA status register (DMAO_SR).
4.
In
the channel control register (DMAO_CRn):
a.
Optionally enable the DMA buffer, SEN=1.
b.
Optionally enable parity checking, PCE=1.
c.
Set the destination address increment,
DAI=1
.
d.
Set the transfer mode
to
peripheral,
TM=ObOO.
e.
Set the peripheral location to external,
PL=O.
f.
Set the transfer direction to peripheral-to-memory, TD=1.
Preliminary Direct Memory Access Controller 18-19
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