Chapter
5.
On-Chip Memory
The on-chip memory (OCM) subsystem consists of a memory controller that connects the
PPC405GP processor core to a one-port, 4KB on-chip SRAM array. OCM is ideal for applications
requiring low-latency access to critical instructions and data.
OCM can provide performance that is
identical to cache hits, yet, unlike a cache, the
OCM never misses. Instructions and data stored
in
the
OCM are always available because OCM contents only change under program control. Therefore, if
the programmer avoids instruction-side and data-side
OCM access contention, OCM can provide
information availability that is superior to a cache line locking scheme.
OCM is superior because it
can provide single cycle performance identical to cache hits without locking down portions of the
cache. This results
in
more effective cache utilization for the processor.
Instructions and data returned from OCM interface do not flow through the PPC405GP core caches.
The caches remain available for caching from other memory sources accessed across the
PLB
interface. The system designer must ensure that each address has a single access path into the
PPC405GP core for a given software process. Each address that is requested should be found
in
either the OCM address space or the
PLB
address space,
but
not in both.
Code to initialize
OCM should execute
in
non-OCM address space
in
a region marked as non-
cachable. The initialization code should invalidate the cache arrays (in the instruction cache unit
(ICU)
and data cache unit (DCU), as appropriate) to ensure that no addresses to be programmed as OCM
space are
in
the cache. After programming the OCM address and control registers, the OCM address
space should remain marked as non-cachable. Chip initialization for
OCM usage is described
in
"OCM Initialization" on page 8-13.
Read and write accesses to the
OCM array share a single access port. OCM accesses have the
following priorities:
1.
Data-side OCM reads (loads)
2. Data-side OCM writes (stores)
3. Instruction-side OCM read (fetches)
Data-side
OCM reads occur
in
one cycle. Data-side writes also complete
in
one cycle, though they
can be pre-empted by higher priority data-side reads.
Instruction-side OCM reads occur by default
(that is, after a reset)
in
two cycles. However, when the Instruction-Side Two-Cycle Mode field of the
OCM Instruction-Side Control Register is set to 0 (OCMO_ISCNTL[ISTCM] = 0), instruction-side OCM
reads occur
in
one cycle, unless pre-empted by higher priority data-side transfers. Two-cycle mode is
provided for chips that cannot make instruction-side timing to the processor core. The
PPC405GP,
however, meets the timing requirement. Therefore, programmers should set
OCMO_ISCNTL[ISTCM] = 0 during chip initialization, as described
in
"OCM Initialization" on
page 8-13.
5.1
OeM Addressing
The address space for the instruction-side OCM and the data side OCM are defined by the OCM
Instruction-Side
Address Range Compare Register (OCMO_ISARC) and OCM Data-Side Address
Range Compare Register
(OCMO_DSARC), respectively. These registers are implemented as 6-bit
registers that define the most significant address bits of the respective
OCM address space. Using 6
Preliminary
On-Chip
Memory
5-1
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