Table 3·15.
PCI
Configuration Registers (continued)
Access
Register Offset
PLB
PCI Description
PCICO_MAXLTNCY
Ox3F R R
PCI Maximum Latency
PCICO_ICS
Ox44
RIW RIW
PCI Interrupt Control/Status
PCICO_ERREN
Ox48
RIW RIW Error Enable
PCICO_ERRSTS
Ox49
RIW RIW Error Status
PCICO_BRDGOPT1 Ox4B-ox4A RIW RIW PCI Bridge Options 1
PCICO_PLBBESRO Ox4F-Ox4C
RIW RIW PLB Slave Error Syndrome 0
PCICO_PLBBESR1
Ox53-0x50
RIW RIW
PLB Slave Error Syndrome 1
PCICO_PLBBEAR
Ox57-0x54
RIW RIW
PLB Slave Error Address Register
PCICO_CAPID
Ox58
R R Capability Identifier
PCICO_NEXTIPTR
Ox59
R R
Next
Item Pointer
PCICO_PMC Ox5B-Ox5A R R Power Management Capabilities
PCICO_PMCSR Ox5D-Ox5C RIW
RIW
Power Management Control Status
PCICO_PMCSRBSE
Ox5E
R R
PMCSR PCI to PCI bridge Support Extensions
PC
I
CO_DATA
Ox5F
-
-
Unused Data
PCICO_BRDGOPT2
Ox63-0x60
R/W
RIW
PCI Bridge Options 2
PCICO_PMSCRR
Ox64
RIW RIW
Power Management State Change Request
Register
3.4 Data Types and
Alignment
The data types consist of bytes (eight bits), halfwords (two bytes), words (four bytes), and strings
(1
to
128 bytes). Figure
3-10 shows the byte, halfword, and word data types and their bit and byte
definitions for big endian representations of
values. Note that PowerPC bit numbering is reversed
from industry conventions; bit
0 represents the most significant bit of a value.
Byte
I
0 2
3
Word
Bit
0
31
I
0
Halfword
0
15
I
0
I
Byte
0
7
Figure 3·10.
PPC405GP Data Types
Data
is
represented
in
either twos-complement notation or
in
an unsigned integer format; data
representation is independent of
alignment issues.
The address of an a data object is
always the lowest address of any byte comprising the object.
All instructions are words, and are word-aligned (the lowest byte address is divisible by 4).
3-26
. PPC405GP User's Manual
Preliminary
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