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IBM PowerPC 405GP User Manual

IBM PowerPC 405GP
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Chapter
4.
Cache Operations
The PPC405GP incorporates two internal caches, a16KB instruction cache and an 8KB data cache.
Instructions and data can be accessed in the caches much faster than
in
main memory.
The instruction cache unit
(ICU) controls instruction accesses to main memory and stores frequently
used instructions to reduce the overhead of instruction transfers between the instruction pipeline and
external memory. Using the instruction cache minimizes access latency for frequently executed
instructions.
The data cache unit (DCU) controls data accesses to main memory and stores frequently used data
to reduce the overhead of data transfers between the GPRs and external memory. Using the data
cache minimizes access latency for frequently used data.
The
ICU features:
โ€ข Programmable address pipelining and prefetching for cache misses and non-cachable lines
โ€ข
Support for non-cachable hits from lines contained
in
fill buffer
โ€ข Programmable non-cachable requests to memory as 4
or
8 words (line
or
half line)
โ€ข Bypass path for critical words
โ€ข Non-blocking cache for hits during fills
โ€ข
Flash invalidate (one instruction invalidates entire cache)
โ€ข Programmable allocation for fetch fills, enabling program control of cache contents using the icbt
instruction
โ€ข Virtually indexed, physically tagged cache arrays
โ€ข Support for 64-bit and 32-bit PLB slaves
โ€ข A rich set of cache control instructions
The DCU features:
โ€ข Address pipelining for line fills
โ€ข Support for load hits from non-cachable and non-allocated lines contained
in
fill buffer
โ€ข Bypass path for critical words
โ€ข Non-blocking cache for hits during fills
โ€ข
Write-back and write-through write strategies controlled by storage attributes
โ€ข Programmable non-cachable load requests to memory as lines
or
words.
โ€ข Handling of up to two pending line flushes.
โ€ข Holding of up to three stores before stalling the core pipeline
โ€ข Physically
indexed, physically tagged cache arrays
โ€ข Support for 64-bit and 32-bit PLB slaves
โ€ข A rich set of cache control instructions
"ICU Organization" on page 4-2 and "DCU Organization" on page 4-5 describe the organization and
provide overviews of the
ICU and the DCU.
Preliminary
Cache Operations
4-1

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IBM PowerPC 405GP Specifications

General IconGeneral
BrandIBM
ModelPowerPC 405GP
CategoryComputer Hardware
LanguageEnglish

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