1
0
Figure 18-6. DMA Source
Address
Registers (DMAO_SAO-DMAO_SA3)
Source address for memory-to-memory
and memory-to-peripheral transfers.
18.3.6 DMA Destination Address Registers (DMAO_DAO-DMAO_DA3)
31
1
The DMA Destination Address Registers (DMAO_DAO-DMAO_DA3) contain the destination address
for memory-to-memory and peripheral-to-memory transfers. When a DMA
channel is configured for
scatter/gather transfers (DMA_SGC[SSGnJ=1) the destination address register is
automatically
loaded
from memory. For additional details see "Scatter/Gather Transfers" on page 18-16.
The destination address must be
aligned at the transfer width programmed
in
DMAO_CRn[TW],
otherwise the error bit
(DMAO_SR[Rln]) is set for the channel and no transfer occurs. If the destination
address increment bit
in
the channel's control register is set (DMAO_CRn[DAI]) the address is
incremented by the transfer width after each data transfer. However, if the
channel is performing a
peripheral-to-memory transfer and the address decrement bit is set (DMAO_CRn[DEC]=1), the
destination address is decremented by the transfer width after each transfer.
1
0
31
1
Figure 18-7. DMA Destination Address Registers (DMAO_DAO-DMAO_DA3)
0:31 Destination address for memory-to-
memory and peripheral-to-memory
transfers.
18.3.7 DMA
Count
Registers (DMAO_CTO-DMAO_CT3)
The DMA Count Registers (DMAO_CTO-DMAO_CT3) contain the number of transfers left
in
the DMA
transaction for their respective
channels when EOTn[TCn] is programmed as a terminal count output.
When EOTn[TCn] is programmed as an end-of-transfer input (DMAO_CRn[ETD]=1),
DMAO_CTn
continues to count down past zero until EOTn is asserted.
Preliminary Direct Memory Access Controller
18-11
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