19:21 PHC Peripheral Hold Cycles
The number of PerClk cycles between
0-7
the time that DMAAckn becomes inactive
until the
peripheral bus is available for the
next bus access. Used
only during the
peripheral side of peripheral mode
transfers.
22
ETD End-of-TransferfTerminal Count (EOTn[TCn])
ETD must be set to 1 if the
channel is
Pin Direction configured for software-initiated memory-
o EOTn[TCn] is an EOT input to-memory transfers.
1 EOTn[TCn] is a TC output
23 TCE
Terminal Count (TC) Enable
If TCE=1, it is required that ETD=1.
o Channel does not stop when TC is reached
1
Channel stops when TC is reached
24:25
CP Channel Priority
Actively requesting channels of the same
00 Low priority
priority are ranked
in
order by channel
01
Medium low priority number, channel 0 having the highest
10 Medium high priority priority. See "Channel Priorities" on
11
High priority
page 18-13 for more information.
26:27
PF Memory Read Prefetch Transfer
Used only during memory-to-peripheral
00 Prefetch 1 doubleword and deviced-paced memory-to-memory
01
Prefetch 2 doublewords transfers.
To
enable prefetching it is
10 Prefetch 4 doublewords required that BEN=1.
11
Reserved
28
PCE Parity Check Enable Enables parity checking for peripheral
o Disable parity checking mode transfers. See "Data Parity During
1
Enable parity checking
DMA
Peripheral Transfers" on
page 18-14.
29 DEC Address Decrement
If DEC=1, it is required that
BEN=O.
This
o SAl and DAI fields control memory address field is valid only for peripheral mode
incrementing.
transfers
(TM=OO).
1 After each data transfer the memory address
is decremented by the transfer width .
30:31
.
...
...
Reserved
.....
...
18.3.5 DMA Source Address Registers (DMAO_SAO-DMAO_SA3)
The DMA Source Address Registers (DMAO_SAO-DMAO_SA3) contain the source address for
memory-to-memory and memory-to-peripheral transfers.
If
a DMA channel is setup for scatter/gather
transfers (DMA_SGC[SSGnl=1) the source address register is automatically loaded from memory.
For additional details see "Scatter/Gather Transfers" on page 18-16.
The source address must be aligned at the transfer width programmed
in
DMAO_CRn[TW], otherwise
the error bit (DMAO_SR[Rln]) is set for the channel and no transfer occurs.
If the source address
increment bit
in
the channel's control register is set (DMAO_CRn[SAI]) the address is incremented by
the transfer width after each data transfer.
In contrast, if the channel is performing a memory-to-
peripheral transfer and the address decrement bit is set (DMAO_CRn[DEC]=1), the address is
decremented by the transfer width after each transfer.
18-10
PPC405GP User's Manual Preliminary
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