IBM PowerPC 405GP User Manual

3.2.1 Physical Address Map
Table 3-1 illustrates the physical address map.
Table 3-1. PPC405GP Address Space
Start End
Function Address Address
Size
Local Memory/Peripherals
1
OxOOOOOOOO Ox7FFFFFFF 2GB
PCI Bridge (Total)
Ox80000000 OxEF5FFFFF 1.744GB
PCI Memory
Ox80000000
OxE7FFFFFF
1.625GB
PCII/O OxE8000000 OxE800FFFF 64KB
Reserved
..
OxE8010000 OxE87FFFFF 8MB-64KB
.
PCII/O OxE8800000 OxEBFFFFFF 56MB
Reserved
(PC1.does not respond)
:
OxECOOOOOO OxEEBFFFFF 44MB
..
PCI Configuration Registers OxEECOOOOO OxEECOOOO7 8B
Reserved
.
..
OxEECOOOO8
...
1MB-8S· .. ':'.
.... : ..... .
..
PCI Interrupt Acknowledge (read) OxEEDOOOOO OxEEDOOO03 4B
PCI Special Cycle (write)
OxEEDOOOOO
OxEEDOOO03 4B
Reserved
.
' .
OxEEDOOOO4 OxEEDFFFFF 1MB4B
': '.:
.
.'
' ...
.. '
Reserved(PCI does not respond) .
.... ..
OxEEEOOOOO
.•. OxEF3F FFFF
6MB
.':.
PCI Local Configuration Registers OxEF400000 OxEF40003F
64B
I
Reserved·.···
'.
....
OxEF400040
OxEF5FFFFF
2MB-64B
.'.
:
.. :
.:.
'.:":
Internal Peripherals (Total)
OxEF600000 OxEFFFFFFF 10MB
UARTO Registers
OxEF600300 OxEF600307 8B
UART1 Registers
OxEF600400 OxEF600407 8B
IIC Registers OxEF600500
OxEF600510
17B
OPB Arbiter Registers OxEF600600 OxEF600601 2B
GPIO Controller Registers
OxEF600700 OxEF60077F 128B
Ethernet
MAC Registers
OxEF600800 OxEF600867 104B
Expansion ROM
2
OxFOOOOOOO OxFFDFFFFF 254MB
Boot
ROM
2
, 3
OxFFEOOOOO OxFFFFFFFF 2MB
1. The local memory/peripheral area of the memory map can be configured for SDRAM, ROM, or peripherals.
2. The boot ROM and expansion ROM areas of the memory map are intended for ROM or flash devices. The
controller supports volatile memory devices such as SDRAM and SRAM in these areas.
3. When booting from PCI memory, the boot ROM address space begins at OxFFFE 0000 (size is 128KB).
3-2 PPC405GP User's Manual Preliminary
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IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English