IBM PowerPC 405GP User Manual

mtspr
isync
b back
CCRO, RN ! Update CCRO.
! Refetch instructions under new processor context.
! Branch back to initialization code.
CCRO[DPP1, UOXE] affect DCU operation. When these fields are altered, execution of the following
code sequence (Sequence 2) is required. Note that Sequence 1 includes Sequence 2, so Sequence
1 can
be used to alter any CCRO fields.
In the following sample code, registers RN, RM, RX, and RZ are any available GPRs.
!
SEQUENCE 2 Alter CCRO[DPP1, UOXE)
! Turn off interrupts
mfmsr' RM
addis RZ,rO,Ox0002 ! CE bit
ori
RZ,RZ,Ox8000 ! EE bit
andc
RZ,RM,RZ! Turn off MSR[CE,EE]
mtmsr
RZ
! sync
sync
!
Alter CCRO bits
mfspr
RN,CCRO ! Read CCRO.
andi/ori RN,RN,OxXXXX ! Execute and/or function to change any CCRO bits.
mtspr
CCRO, RN ! Update CCRO.
isync ! Refetch instructions under new processor context.
! Restore
MSR to original value
mtmsr RM
CCRO[CIS, CWS] do not require special programming.
4.4.2 leu Debugging
The icread instruction enables the reading of the instruction cache entries for the congruence class
specified by EA
19
:
26
.
The cache information is read into the ICDBDR; from there it can subsequently
be moved, using a mfspr instruction, into a GPR.
10 3
1
1
Figure 4-3. Instruction Cache Debug Data Register (ICDBDR)
Instruction cache information
See icread, page 24-68.
4-14
PPC405GP User's Manual Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English