IBM PowerPC 405GP User Manual

1 cycle, asynchronously to the corresponding write data beat on the PLB. For connected writes, a
PLB bus error
signal is asserted with the data transfer, and the data is discarded. If
PCICO_ERREN[MAEE)
= 0, error reporting is masked. No PLB bus error signal is asserted,
regardless of the setting of PCICO_ERREN[MEAE).
The following status bits are set:
1.
If a master abort is signalled, PCICO_STATUS[RMA) = 1. Setting of this field is non-maskable.
Writing a 1 to PCICO_STATUS[RMA) resets the field.
2. If master abort is detected as an error, PCICO_ERREN[MEAE) is set to 1 to indicate an event that
would cause a PLB bus error to be asserted by the bridge PLB slave, regardless of the setting of
PCICO_ERREN[MEAE). This field can be reset by writing a 1 to PCICO_ERREN[MEAE).
3. PCICO_PLBBEAR and PCICO_PLBBESRx are updated as follows:
The address of the aborted request is saved in PCICO_PLBBEAR if all
PCICO_PLBBESRx[MxAL)
= ° (PCICO_PLBBEAR is unlocked). If all
PCICO_PLBBESRx[MxFL)
= 0, PCICO_PLBBESRx[MxET) = Ob1 01 to indicate a non-configured
bank error; and
PCICO_PLBBESRx[MxRWS) is set to ° on a write, 1 on a read. If
PCICO_ERREN[MAEE)
= ° or PCICO_ERREN[MEAE) = 0, no PCICO_PLBBEAR or
PCICO_PLBBESRx update is performed.
17.6.3 Bridge PCI Master Receives Target Abort While PCI Bus Master
This error is generated when the bridge PCI master receives a target abort while mastering a cycle on
the
PCI bus. Upon detection of this error, the bridge PLB slave may assert a PLB bus error signal on
the PLB
in response to this error, as explained below.
Two masks are associated with a target abort. PCICO_ERREN[TAEE) masks error reporting. If the
error is detected, a PLB bus error
signal is asserted if PCICO_ERREN[TAEE) = 1. For reads, the
bridge PLB
slave still completes the transfer on the PLB and drives the appropriate PLB bus error line
for each data beat (note that for line reads, a PLB bus error signal is asserted for all data beats). For
posted writes, if
PCICO_ERREN[TAEE) = 1, the bridge PLB slave asserts a PLB bus error for 1 cycle,
asynchronously to the corresponding write data beat on the PLB. For connected writes, a PLB bus
error
signal is asserted with the data transfer, and the data is discarded. If PCICO_ERREN[TAEE) = 0,
error reporting is masked No PLB bus error signal is asserted, regardless of the setting of
PCICO_ERREN[MEAE). If prefetching is occurring when a target abort is received, data preceding the
target abort is kept
in a prefetch buffer.
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PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English