TCI=1 and DMAO_CRn[TCE]=1 and DMAO_SR[CSn]=1
ETI=1 and DMAO_SR[TSn]=1
ERI=1 and DMAO_SR[Rln]=1
For both normal DMA and scatter/gather transfers the interrupt remains active until the appropriate
bits are
cleared
in
the DMA Status Register (DMAO_SR).
In
addition, interrupts from a channel
performing a scatter/gather transfer cause the channel to pause until the interrupt is cleared.
18.8 Scatter/Gather Transfers
With a normal DMA transfer it is necessary to program a channel's control, source, destination, and
count registers for each transfer. The scatter/gather capability of the DMA
controller provides a more
efficient
solution for applications that require multiple transactions on a single DMA channel. Instead
of individually programming a channel's registers, software creates a set (linked list) of descriptor
tables
in
system memory. Table 18-5 illustrates the required table format.
Table 18-5. Scatter/Gather Descriptor Table
Memory
Address
Byte
0
I
Byte
1
I
Byte
2 I
Byte
3
(MSB)
(LSB)
x (word aligned)
DMA Channel Control Word
x+4
Source Address
x+8
Destination Address
x + 12
LK
I I TCI I ETI I ERI I
...
I
.
I
Count
x + 16 Next Scatter/Gather Descriptor
Table Address
Table 18-6 details the usage of the bit fields
in
the scatter/gather table.
Table 18-6.
Bit
Fields in the Scatter/Gather Descriptor Table
Bit
Mnemonic
Description
0
LK
Link
o This is the last descriptor.
1 Fetch next descriptor from address
DMAO_SGn when the channel completes
2 TCI
Enable Terminal
Count Interrupt
o Do not interrupt when terminal count occurs
1
Allow an interrupt when terminal count occurs
3
ETI
Enable
End of Transfer Interrupt
o Do not interrupt when end of transfer occurs
1
Allow an interrupt when end of transfer occurs.
4
ERI
Enable
Error Interrupt
o Do not interrupt if an error occurs
1
Allow an interrupt if an error occurs
To
configure a channel for a scatter/gather transfer the DMA Scatter/Gather Descriptor Address
Register (DMAO_SGn) for the
channel is set to the address of the first descriptor table, which must be
word-aligned.
To
begin the scatter/gather transfer, software then writes a start scatter/gather and
enable mask to the Scatter/Gather Command Register (DMAO_SGC). The DMA controller then reads
the descriptor
table at address DMAO_SGn and updates the DMA controller registers as shown
in
18-16
PPC405GP User's Manual
Preliminary
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