!he
following status bits are set:
1. If a target abort is received, PCICO_STATUS[RTA]
=
1.
Setting this field is non-maskable. Writing a
1 to PCICO_STATUS[RTA] clears the field.
2.
If
a target abort is detected as an error, PCICO_ERRSTS[MEAE] = 1 to indicate an event that
would cause the bridge PLB slave to assert a PLB bus error signal, regardless of the setting of
PCICO_ERREN[MEAE]. Writing a 1 to PCICO_ERRSTS[MEAE] resets the field.
3. PCICO_PLBBEAR and PCICO_PLBBESRx are updated as
follows:
The address of the aborted request is saved
in
PCICO_PLBBEAR if all
PCICO_PLBBESRx[MxAL] = 1 (PCICO_PLBBEAR is unlocked). If all
PCICO_PLBBESRx[MxFL] =
1,
PCICO_PLBBESRx[MxET] =
Ob101
to indicate a nonconfigured
bank error, and PCICO_PLBBESRx[MxRWS] is set to
° on a write, or to 1 on a read. If
PCICO_ERREN[MAEE]
= °
or
PCICO_ERREN[MEAE] =
0,
no PCICO_PLBBEAR
or
PCICO_PLBBESRx update is performed.
17.6.4 PCI Target Data Bus Parity Error Detection
This error is generated when the bridge PCI target detects a data bus parity error on write data from a
PCI master
dOing
a write cycle to PLB memory. PCI uses even parity.
Setting PCICO_CMD[PER]
= ° masks this error.
The
following status bits are set:
1. PCICO_STATUS[DEPE]
= 1 to indicate a PCI bus parity error. Setting this field is non-maskable.
Writing a 1 to PCICO_STATUS[DEPE] clears the field.
2. PCICO_STATUS[SSE]
= 1 if PCICO_ERREN[WDPE] =
1.
Writing a 1 to PCICO_STATUS[SSE]
clears the field.
3. PCICO_ERRSTS[WDPE]
= 1 if PCICO_ERREN[WDPE] = 1. Writing a 1 to PCICO_STATUS[SSE]
clears the field.
17.6.5 PCI Master Data Bus Parity Error Detection
This error is generated when a data bus parity error is detected on the PCI bus during a cycle
mastered by the bridge PCI master. The bridge PCI master checks parity on read cycles and samples
PCIPErr on write cycles. The bridge PCI master may assert PCIPErr if the master detects a parity
error on a read. PCI uses even parity.
Setting PCICO_CMD[PER]
= ° masks this error. PCICO_STATUS[DEPE] = 1. If a parity error is
detected, writing a 1 to PCICO_STATUS[DEPE]
= 1 clears the field.
If PCICO_ERREN[MEAE]
= 1 and the error is detected as described, the PLB slave asserts a PLB
error signal on the PLB in response to the error. For reads, a PLB bus error is asserted for each data
beat in which bad parity
was detected. For writes, a PLB bus error is asserted for each data beat
in
which bad parity was detected, but asynchronously to the actual transfer of write data on the PLB.
Preliminary
PCllnterface
17-57
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