4:5
..โข
Reserved
6:8
EET1
Error type for master 1
Master
1
is
the
processor
data
side.
000 No error
001
Reserved
01
X
EGG
uncorrectable error
1 XX Reserved
9
RWS1
Read/write status for master 1
o Error operation was a write operation
1 Error operation was a read operation
10:11
Reserved
..
12:14 EET2 Error type for master 2
Master
2
is
the
external
bus
master.
000 No error
001
Reserved
01X
EGG
uncorrectable error
1 XX Reserved
15
RWS2 Read/write status for master 2
o Error operation was a write operation
1 Error operation was a read operation
16:17
Reserved
.>
18:20 EET3 Error type for master 3
Master
3
is
the
PCI
bridge.
000 No error
001
Reserved
01
X
EGG
uncorrectable error
1 XX Reserved
21
RWS3 Read/write status for master 3
o Error operation was a write operation
1 Error operation was a read operation
22 FL3
Field lock for master 3
o EET3 and RWS3 fields are unlocked
1 EET3 and RWS3 fields are locked
23 AL3 SDRAMO_BEAR address lock for master 3
o SDRAMO_BEAR address unlocked
1 SDRAMO_BEAR address locked
24:31
.>
.....
i.>
.....
Reserved
15.4.8 Bus Error Syndrome Register 1 (SDRAMO_BESR1)
This register tracks errors encountered during MAL and DMA accesses to SDRAM memory. Bits
in
SDRAMO_BESR1 are cleared by writing a 32-bit value to SDRAMO_BESR1 with a 1
in
any bit
position that is to be cleared and
ยฐ in all other bit positions.
15-18
PPG405GP User's Manual Preliminary