In
a mfspr
or
mtspr instruction, the 1
O-bit
SPRN field specifies the SPR number of the source
or
destination SPR. The SPRN field contains two five-bit subfields, SPRN
o
:
4
and SPRN
s
:
9
. The
assembler handles the unusual register number encoding to generate the
SPRF field.
In
the machine
code for the
mfspr and mtspr instructions, the SPRN subfields are reversed (ending up as SPRF
s
:
9
arid SPRF
o
:
4
)
for compatibility with the POWER Architecture.
In
the PowerPC Architecture, SPR numbers having a 1
in
the most-significant bit of the SPRF field are
privileged.
The
following example illustrates how SPR numbers appear
in
assembler language coding and in
machine coding of the
mfspr and mtspr instructions.
In assembler language coding,
SRRO
is SPR 26. Note that the assembler handles the unusual
register number encoding to generate the
SPRF field.
mfspr r5,26
When the
SPR number is considered as a binary number
(ObOOOOO
11
01
0), the most-significant bit is
O.
However, the machine code for the instruction reverses the subfields, resulting
in
the following
SPRF
field:
Ob11
01
000000. The most-significant bit is 1;
SRRO
is privileged.
When an
SPR number is considered as a hexadecimal number, the second digit of the three-digit
hexadecimal number indicates whether an
SPR is privileged. If the second digit
is
odd
(1,3,5,7,9,
B,
D,
F), the SPR is privileged.
For example, the
SPR number of
SRRO
is 26
(Ox01
A). The second hexadecimal digit is odd;
SRRO
is
privileged.
In contrast, the LR is SPR B
(OxOOB);
the second hexadecimal digit is not odd; the LR is
non-privileged.
3.9.4 Privileged DCRs
The mtdcr and mfdcr instructions themselves are privileged,
in
all cases. All
DCRs
are privileged.
3.10 Synchronization
The PPC405GP supports the synchronization operations of the PowerPC Architecture. The following
book, chapter, and section numbers refer
to
related information
in
The PowerPC Architecture: A
Specification for
a
New
Family
of
RISC Processors:
• Book II, Section
1.B.1,
"Storage Access Ordering" and "Enforce In-order Execution of
1/0"
• Book III, Section 1.7, "Synchronization"
• Book III, Chapter 7, "Synchronization Requirements for Special Registers and Lookaside Buffers"
Preliminary
Programming
Model
3-43
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