IBM PowerPC 405GP User Manual

3 MED PLB Bus Error Detected
Set when a
PLB bus error signal is
1 Error detected
asserted when
PCI bridge is the PLB
master. MED is set regardless of whether
the
PCI bridge is enabled to treat this as an
error condition (the setting
of MED is not
maskable).
2 MEAE
PLB Bus Error Assertion Event
Set when an error occurs that would cause
1
An PCI bridge error, which can cause a
PCI bridge (as PLB slave) to assert a PLB
PLB bus error, occurred.
bus error signal. MEAE is set regardless of
whether the the
PLB bus error assertion is
enabled (the setting of MEAE is not
maskable).
1
WDPE PCISerr on Write Data Parity Error
Set when the PCI bridge drives PCISErr
in
response to a data parity error detected on
a
PCI write to PLB memory. PCIPErr is
also driven.
0
PUR
PLB Unsupported Request
Set when the PCI bridge is a PLB slave
and detects an unsupported request from
a
PLB master to an address range that PCI
bridge decodes. The PCI bridge allows
such requests to time out.
17.5.3.26 Bridge Options 1 Register (PCICO_BRDGOPT1)
PCICO_BRDGOPT1 controls various operating parameters of the PCI bridge. The parameters must
be initialized before
PCI masters access the PCI bridge.
PLMTCR
..
PRP PAPM APLRM
.. .. ..
f f f
PLESE PGMAE PTMRCI
Figure 17-47. Bridge Options 1 Register (PCICO_BRDGOPT1)
15:8 PMLTCR
PLB Master Latency Timer Count Register
PMLTCR contains the value used by the
PLB master to load its latency timer. The
granularity of this timer is 16 PLB cycles;
therefore, the low-order bits of this
register are
read-only and are hardwired
to
1.
7 PLESE
PLB Lock Error Status Enable
PLESE controls the handling of slave
o Slave error locking is disabled.
error locking.
1 Slave error locking is enabled.
17-44
PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English