IBM PowerPC 405GP User Manual

3.11.6.3 Shift Instructions
These instructions rotate operands stored in the GPRs.
Table
3-31 lists the PPC405GP shift instructions. Shift right algebraic instructions implicitly update
XER[CA].
In the table, the syntax "[.]" indicates that the instruction has a "record" form that updates
CR[CRO], and a "non-record" form.
Table 3-31. Shift Instructions
Shift Right
Shift Left Shift Right Algebraic
slw[.] srw[.]
sraw[.]
srawi[.]
3.11.6.4 Cache Management Instructions
These instructions control the operation of the ICU and DCU. Instructions are provided to fill or
invalidate instruction cache blocks. Instructions are also provided to fill, flush, invalidate, or zero data
cache blocks, where a block is'defined as a 32-byte cache line.
Table 3-32
lists the PPC405GP cache management instructions.
Table 3-32. Cache Management Instructions
Deu leu
deba
leb!
debf
lebt
deb
I leeei
debst
leread
debt
debtst
debz
deeel
deread
3.11.7 Interrupt Control Instructions
mfmsr and mtmsr read and write data between the MSR and a GPR to enable and disable
interrupts.
wrtee and wrteei enable and disable external interrupts. rfi and rfci return from interrupt
handlers. Table 3-33 lists the
PPC405GP interrupt control instructions.
3-52
Table 3-33. Interrupt Control Instructions
mfmsr
PPC405GP User's Manual
mtmsr
rfi
rfei
wrtee
wrteei
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English