The
range
of
PCI
memory
address
space
associated with each PMM is also programmable,
and
is a
64-bit address
space
to
enable address translation between the PCI bus and the PLB.
The
PCILO_PMMnPCILA registers contain the low-order word
of
a PCI address; the PCILO_PMMnPCIHA
registers contain the high-order word
of
a PCI address.
If
the high-order word
of
a PCI
address
is
greater than
0, the PCI bridge generates dual address cycles to the PCI.
The
size
of
each
PMM
is programmable, using the
mask
portion
of
the PCILO_PMMnMA registers.
The
size is a
power
of
2, ranging from
4KB-4GB.
The
PLB
and
PCI address spaces for each
PMM
are
aligned to the size contained in the associated PCILO_PMMnMA registers.
The
attribute portion
of
the PCILO_PMMnMA registers specify
whether
the associated
PMM
is
enabled
or
disabled,
and
marked
as
prefetchable
or
not
prefetchable.
Address ranges
and
attributes should be initialized before a PMM is enabled.
Figure 17-5 shows the detail
of
the PMM register sets
used
to
map
PLB
memory
regions to PCI
address space.
PMM#
PMM
# Local Address
PMM
# Mask/Attribute
1
Size
PLB Memory
PCI
Memory Size
1
Region
L....-----T
PMM#PCI
Low Address
Region
J
./r~--------'
Starting Address
PMM#PCI
High Address
Figure 17-5.
PMM
Register Sets Map PLB Address Space
to
PCI
Address Space
17.3.2 PCI-to-PLB Address Mapping
The
PCI bridge responds
as
a PCI target for
memory
accesses
and
configuration Type ° accesses.
Table 17-4 shows the PCI
memory
address
map
from the view
of
PCI, that is,
as
decoded
by the PCI
bridge as a PCI target.
Table 17-4.
PCI
Memory Address Map
PCI
Memory
Address
Description
PLB Address
OxOOOOOOOO-
System Memory or
ROM-Range
0
OxOOOOOOOO-
OxFFFFFFFF
PTM
1 maps a region of
PCI
memory space to
PLB
space, which
can
OxFFFFFFFF
map
to
system memory or
ROM.
Size and location
is
programmable.
The space supports address translation between the
PCI
and
the
PLB.
OxOOOOOOOo-
System Memory or
ROM-Range
1
OxOOOOOOOo-
OxFFFFFFFF
PTM
2 maps a region of
PCI
memory space
to
PLB
space, which
can
OxFFFFFFFF
map to system memory or
ROM.
Size and location is programmable.
The space supports address translation between the
PCI
and
the
PLB.
17-8
PPC405GP User's Manual
Preliminary
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