•
In
the problem state with data translation enabled:
- A zone fault, which is any user-mode storage access (data load, store, iebi, debz,
debst,
or
debf) with an effective address with (ZPR
field) = 00.
(debt
and
debtst
will no-op
in
this
situation, rather than cause an interrupt. The instructions debi, deeei, iebt, and ieeei, being
privileged, cannot cause zone fault data storage interrupts.)
- Data store or
debz
to an effective address with the WR bit clear and (ZPR field)
-:j:
11. (The
privileged instructions
debi
and deeei are treated as "stores," but will cause privileged program
interrupts, rather than data storage interrupts.)
•
In
the supervisor state with data translation enabled:
- Data store, debi, debz, or deeei to an effective address with the WR bit clear and (ZPR field)
other than
11
or 10.
Programming
Note: The iebi, iebt, and ieeei instructions are treated as loads from the
addressed byte with respect to address
translation and protection. Instruction cache operations
use MSR[DR], not
MSR[IR], to determine translation of their operands. Instruction storage
interrupts and Instruction-side TLB Miss
Interrupts are associated with the fetching of instructions,
not with the execution of instructions. Data storage interrupts and data TLB miss interrupts are
associated with the
execution of instruction cache operations.
When a data storage interrupt is detected, the
PPC405GP suppresses the instruction causing the
interrupt and writes the instruction address
in
SRRO.
The Data Exception Address Register (DEAR) is
loaded with the data address that caused the access violation. ESR bits are loaded as shown
in
Table 10-10, "Register Settings during Data Storage Interrupts," on page 10-37
to
provide further
information about the error. The current contents of the
MSR are loaded into SRR1, and MSR bits are
then
loaded with the values shown
in
Table 10-10.
The high-order 16 bits of the program counter are then loaded with the contents of the EVPR and the
low-order 16 bits of the program counter are loaded with Ox0300. Interrupt processing begins at the
new address
in
the program counter. Executing the return from interrupt instruction (rfi) restores the
contents of the program counter and the
MSR from
SRRO
and SRR1, respectively, and the
PPC405GP resumes execution at the new program counter address.
For instructions that can
simultaneously generate program interrupts (privileged instructions executed
in
Problem State) and data storage interrupts, the program interrupt has priority.
Table 10-10.
Register
Settings
during
Data
Storage
Interrupts
SRRO
Written with the EA of the instruction causing the data storage interrupt
SRR1
Written with the value of the MSR at the time of the interrupt
MSR
WE,
EE,
PR, DWE, IR,
DR~O
CE, ME, DE
~
unchanged
PC EVPR[0:15]
II
Ox0300
DEAR
Written with the EA of the
failed access
ESR DST
~
1 if excepting operation is a store (includes
dcbi
and dcbz)
DIZ
~
1 if access failure caused by a zone protection fault (ZPR[Zn] = 00 in
user mode)
UOF
~
1 if access failure caused by a
UO
fault (the
UO
storage attribute is
set and
CCRO[UOXE]
= 1)
MCI
~
unchanged
All other bits are cleared.
Preliminary Interrupt Controller
Operations 10-37
To Next Page
Loading...
Need help?
General
